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The verilator simulation interface uses the remote_bitbang protocol from openocd. I have a simple implementation for urjtag too. Signed-off-by: Anton Blanchard <anton@linux.ibm.com>caravel-20210105
6 changed files with 1207 additions and 19 deletions
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|
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-- JTAG to DMI interface, based on the Xilinx version |
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-- |
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-- DMI bus |
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-- |
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-- req : ____/------------\_____ |
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-- addr: xxxx< >xxxxx, based on the Xilinx version |
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-- dout: xxxx< >xxxxx |
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-- wr : xxxx< >xxxxx |
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-- din : xxxxxxxxxxxx< >xxx |
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-- ack : ____________/------\___ |
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-- |
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-- * addr/dout set along with req, can be latched on same cycle by slave |
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-- * ack & din remain up until req is dropped by master, the slave must |
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-- provide a stable output on din on reads during that time. |
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-- * req remains low at until at least one sysclk after ack seen down. |
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-- |
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-- JTAG (tck) DMI (sys_clk) |
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-- |
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-- * jtag_req = 1 |
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-- (jtag_req_0) * |
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-- (jtag_req_1) -> * dmi_req = 1 > |
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-- *.../... |
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-- * dmi_ack = 1 < |
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-- * (dmi_ack_0) |
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-- * <- (dmi_ack_1) |
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-- * jtag_req = 0 (and latch dmi_din) |
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-- (jtag_req_0) * |
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-- (jtag_req_1) -> * dmi_req = 0 > |
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-- * dmi_ack = 0 < |
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-- * (dmi_ack_0) |
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-- * <- (dmi_ack_1) |
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-- |
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-- jtag_req can go back to 1 when jtag_rsp_1 is 0 |
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-- |
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-- Questions/TODO: |
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-- - I use 2 flip fops for sync, is that enough ? |
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-- - I treat the jtag_trst as an async reset, is that necessary ? |
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-- - Dbl check reset situation since we have two different resets |
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-- each only resetting part of the logic... |
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-- - Look at optionally removing the synchronizer on the ack path, |
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-- assuming JTAG is always slow enough that ack will have been |
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-- stable long enough by the time CAPTURE comes in. |
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-- - We could avoid the latched request by not shifting while a |
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-- request is in progress (and force TDO to 1 to return a busy |
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-- status). |
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-- |
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-- WARNING: This isn't the real DMI JTAG protocol (at least not yet). |
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-- a command while busy will be ignored. A response of "11" |
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-- means the previous command is still going, try again. |
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-- As such We don't implement the DMI "error" status, and |
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-- we don't implement DTMCS yet... This may still all change |
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-- but for now it's easier that way as the real DMI protocol |
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-- requires for a command to work properly that enough TCK |
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-- are sent while IDLE and I'm having trouble getting that |
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-- working with UrJtag and the Xilinx BSCAN2 for now. |
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|
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library ieee; |
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use ieee.std_logic_1164.all; |
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use ieee.math_real.all; |
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library work; |
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use work.wishbone_types.all; |
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entity dmi_dtm_jtag is |
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generic(ABITS : INTEGER:=8; |
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DBITS : INTEGER:=32); |
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port(sys_clk : in std_ulogic; |
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sys_reset : in std_ulogic; |
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dmi_addr : out std_ulogic_vector(ABITS - 1 downto 0); |
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dmi_din : in std_ulogic_vector(DBITS - 1 downto 0); |
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dmi_dout : out std_ulogic_vector(DBITS - 1 downto 0); |
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dmi_req : out std_ulogic; |
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dmi_wr : out std_ulogic; |
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dmi_ack : in std_ulogic; |
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-- dmi_err : in std_ulogic TODO: Add error response |
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jtag_tck : in std_ulogic; |
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jtag_tdi : in std_ulogic; |
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jtag_tms : in std_ulogic; |
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jtag_trst : in std_ulogic; |
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jtag_tdo : out std_ulogic |
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); |
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end entity dmi_dtm_jtag; |
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architecture behaviour of dmi_dtm_jtag is |
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-- Signals coming out of the JTAG TAP controller |
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signal capture : std_ulogic; |
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signal update : std_ulogic; |
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signal sel : std_ulogic; |
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signal shift : std_ulogic; |
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signal tdi : std_ulogic; |
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signal tdo : std_ulogic; |
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-- ** JTAG clock domain ** |
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-- Shift register |
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signal shiftr : std_ulogic_vector(ABITS + DBITS + 1 downto 0); |
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-- Latched request |
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signal request : std_ulogic_vector(ABITS + DBITS + 1 downto 0); |
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-- A request is present |
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signal jtag_req : std_ulogic; |
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-- Synchronizer for jtag_rsp (sys clk -> jtag_tck) |
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signal dmi_ack_0 : std_ulogic; |
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signal dmi_ack_1 : std_ulogic; |
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-- ** sys clock domain ** |
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-- Synchronizer for jtag_req (jtag clk -> sys clk) |
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signal jtag_req_0 : std_ulogic; |
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signal jtag_req_1 : std_ulogic; |
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|
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-- ** combination signals |
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signal jtag_bsy : std_ulogic; |
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signal op_valid : std_ulogic; |
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signal rsp_op : std_ulogic_vector(1 downto 0); |
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-- ** Constants ** |
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constant DMI_REQ_NOP : std_ulogic_vector(1 downto 0) := "00"; |
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constant DMI_REQ_RD : std_ulogic_vector(1 downto 0) := "01"; |
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constant DMI_REQ_WR : std_ulogic_vector(1 downto 0) := "10"; |
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constant DMI_RSP_OK : std_ulogic_vector(1 downto 0) := "00"; |
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constant DMI_RSP_BSY : std_ulogic_vector(1 downto 0) := "11"; |
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attribute ASYNC_REG : string; |
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attribute ASYNC_REG of jtag_req_0: signal is "TRUE"; |
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attribute ASYNC_REG of jtag_req_1: signal is "TRUE"; |
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attribute ASYNC_REG of dmi_ack_0: signal is "TRUE"; |
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attribute ASYNC_REG of dmi_ack_1: signal is "TRUE"; |
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component tap_top port ( |
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-- JTAG pads |
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tms_pad_i : in std_ulogic; |
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tck_pad_i : in std_ulogic; |
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trst_pad_i : in std_ulogic; |
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tdi_pad_i : in std_ulogic; |
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tdo_pad_o : out std_ulogic; |
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tdo_padoe_o : out std_ulogic; |
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|
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-- TAP states |
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shift_dr_o : out std_ulogic; |
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pause_dr_o : out std_ulogic; |
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update_dr_o : out std_ulogic; |
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capture_dr_o : out std_ulogic; |
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-- Select signals for boundary scan or mbist |
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extest_select_o : out std_ulogic; |
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sample_preload_select_o : out std_ulogic; |
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mbist_select_o : out std_ulogic; |
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debug_select_o : out std_ulogic; |
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-- TDO signal that is connected to TDI of sub-modules. |
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tdo_o : out std_ulogic; |
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-- TDI signals from sub-modules |
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debug_tdi_i : in std_ulogic; |
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bs_chain_tdi_i : in std_ulogic; |
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mbist_tdi_i : in std_ulogic |
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); |
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end component; |
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begin |
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tap_top0 : tap_top |
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port map ( |
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tms_pad_i => jtag_tms, |
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tck_pad_i => jtag_tck, |
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trst_pad_i => jtag_trst, |
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tdi_pad_i => jtag_tdi, |
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tdo_pad_o => jtag_tdo, |
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tdo_padoe_o => open, -- what to do with this? |
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shift_dr_o => shift, |
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pause_dr_o => open, -- what to do with this? |
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update_dr_o => update, |
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capture_dr_o => capture, |
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-- connect boundary scan and mbist? |
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extest_select_o => open, |
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sample_preload_select_o => open, |
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mbist_select_o => open, |
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debug_select_o => sel, |
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tdo_o => tdi, |
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debug_tdi_i => tdo, |
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bs_chain_tdi_i => '0', |
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mbist_tdi_i => '0' |
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); |
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-- dmi_req synchronization |
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dmi_req_sync : process(sys_clk) |
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begin |
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-- sys_reset is synchronous |
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if rising_edge(sys_clk) then |
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if (sys_reset = '1') then |
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jtag_req_0 <= '0'; |
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jtag_req_1 <= '0'; |
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else |
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jtag_req_0 <= jtag_req; |
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jtag_req_1 <= jtag_req_0; |
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end if; |
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end if; |
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end process; |
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dmi_req <= jtag_req_1; |
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|
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-- dmi_ack synchronization |
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dmi_ack_sync: process(jtag_tck, jtag_trst) |
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begin |
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-- jtag_trst is async (see comments) |
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if jtag_trst = '1' then |
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dmi_ack_0 <= '0'; |
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dmi_ack_1 <= '0'; |
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elsif rising_edge(jtag_tck) then |
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dmi_ack_0 <= dmi_ack; |
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dmi_ack_1 <= dmi_ack_0; |
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end if; |
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end process; |
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-- jtag_bsy indicates whether we can start a new request, we can when |
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-- we aren't already processing one (jtag_req) and the synchronized ack |
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-- of the previous one is 0. |
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-- |
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jtag_bsy <= jtag_req or dmi_ack_1; |
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-- decode request type in shift register |
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with shiftr(1 downto 0) select op_valid <= |
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'1' when DMI_REQ_RD, |
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'1' when DMI_REQ_WR, |
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'0' when others; |
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-- encode response op |
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rsp_op <= DMI_RSP_BSY when jtag_bsy = '1' else DMI_RSP_OK; |
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-- Some DMI out signals are directly driven from the request register |
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dmi_addr <= request(ABITS + DBITS + 1 downto DBITS + 2); |
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dmi_dout <= request(DBITS + 1 downto 2); |
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dmi_wr <= '1' when request(1 downto 0) = DMI_REQ_WR else '0'; |
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-- TDO is wired to shift register bit 0 |
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tdo <= shiftr(0); |
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-- Main state machine. Handles shift registers, request latch and |
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-- jtag_req latch. Could be split into 3 processes but it's probably |
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-- not worthwhile. |
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-- |
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shifter: process(jtag_tck, jtag_trst, sys_reset) |
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begin |
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if jtag_trst = '1' or sys_reset = '1' then |
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shiftr <= (others => '0'); |
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jtag_req <= '0'; |
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request <= (others => '0'); |
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elsif rising_edge(jtag_tck) then |
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-- Handle jtag "commands" when sel is 1 |
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if sel = '1' then |
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-- Shift state, rotate the register |
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if shift = '1' then |
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shiftr <= tdi & shiftr(ABITS + DBITS + 1 downto 1); |
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end if; |
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-- Update state (trigger) |
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-- |
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-- Latch the request if we aren't already processing one and |
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-- it has a valid command opcode. |
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-- |
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if update = '1' and op_valid = '1' then |
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if jtag_bsy = '0' then |
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request <= shiftr; |
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jtag_req <= '1'; |
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end if; |
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-- Set the shift register "op" to "busy". This will prevent |
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-- us from re-starting the command on the next update if |
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-- the command completes before that. |
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shiftr(1 downto 0) <= DMI_RSP_BSY; |
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end if; |
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-- Request completion. |
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-- |
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-- Capture the response data for reads and clear request flag. |
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-- |
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-- Note: We clear req (and thus dmi_req) here which relies on tck |
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-- ticking and sel set. This means we are stuck with dmi_req up if |
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-- the jtag interface stops. Slaves must be resilient to this. |
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-- |
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if jtag_req = '1' and dmi_ack_1 = '1' then |
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jtag_req <= '0'; |
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if request(1 downto 0) = DMI_REQ_RD then |
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request(DBITS + 1 downto 2) <= dmi_din; |
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end if; |
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end if; |
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-- Capture state, grab latch content with updated status |
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if capture = '1' then |
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shiftr <= request(ABITS + DBITS + 1 downto 2) & rsp_op; |
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end if; |
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end if; |
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end if; |
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end process; |
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end architecture behaviour; |
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////////////////////////////////////////////////////////////////////// |
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//// //// |
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//// tap_top.v //// |
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//// //// |
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//// //// |
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//// This file is part of the JTAG Test Access Port (TAP) //// |
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//// http://www.opencores.org/projects/jtag/ //// |
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//// //// |
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//// Author(s): //// |
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//// Igor Mohor (igorm@opencores.org) //// |
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//// //// |
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//// //// |
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//// All additional information is avaliable in the README.txt //// |
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//// file. //// |
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//// //// |
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////////////////////////////////////////////////////////////////////// |
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//// //// |
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//// Copyright (C) 2000 - 2003 Authors //// |
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//// //// |
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//// This source file may be used and distributed without //// |
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//// restriction provided that this copyright statement is not //// |
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//// removed from the file and that any derivative work contains //// |
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//// the original copyright notice and the associated disclaimer. //// |
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//// //// |
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//// This source file is free software; you can redistribute it //// |
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//// and/or modify it under the terms of the GNU Lesser General //// |
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//// Public License as published by the Free Software Foundation; //// |
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//// either version 2.1 of the License, or (at your option) any //// |
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//// later version. //// |
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//// //// |
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//// This source is distributed in the hope that it will be //// |
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//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
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//// PURPOSE. See the GNU Lesser General Public License for more //// |
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//// details. //// |
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//// //// |
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//// You should have received a copy of the GNU Lesser General //// |
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//// Public License along with this source; if not, download it //// |
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//// from http://www.opencores.org/lgpl.shtml //// |
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//// //// |
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////////////////////////////////////////////////////////////////////// |
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// |
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// CVS Revision History |
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// |
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// $Log: not supported by cvs2svn $ |
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// Revision 1.5 2004/01/18 09:27:39 simons |
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// Blocking non blocking assignmenst fixed. |
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// |
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// Revision 1.4 2004/01/17 17:37:44 mohor |
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// capture_dr_o added to ports. |
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// |
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// Revision 1.3 2004/01/14 13:50:56 mohor |
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// 5 consecutive TMS=1 causes reset of TAP. |
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// |
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// Revision 1.2 2004/01/08 10:29:44 mohor |
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// Control signals for tdo_pad_o mux are changed to negedge. |
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// |
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// Revision 1.1 2003/12/23 14:52:14 mohor |
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// Directory structure changed. New version of TAP. |
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// |
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// Revision 1.10 2003/10/23 18:08:01 mohor |
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// MBIST chain connection fixed. |
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// |
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// Revision 1.9 2003/10/23 16:17:02 mohor |
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// CRC logic changed. |
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// |
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// Revision 1.8 2003/10/21 09:48:31 simons |
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// Mbist support added. |
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// |
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// Revision 1.7 2002/11/06 14:30:10 mohor |
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// Trst active high. Inverted on higher layer. |
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// |
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// Revision 1.6 2002/04/22 12:55:56 mohor |
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// tdo_padoen_o changed to tdo_padoe_o. Signal is active high. |
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// |
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// Revision 1.5 2002/03/26 14:23:38 mohor |
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// Signal tdo_padoe_o changed back to tdo_padoen_o. |
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// |
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// Revision 1.4 2002/03/25 13:16:15 mohor |
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// tdo_padoen_o changed to tdo_padoe_o. Signal was always active high, just |
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// not named correctly. |
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// |
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// Revision 1.3 2002/03/12 14:30:05 mohor |
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// Few outputs for boundary scan chain added. |
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// |
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// Revision 1.2 2002/03/12 10:31:53 mohor |
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// tap_top and dbg_top modules are put into two separate modules. tap_top |
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// contains only tap state machine and related logic. dbg_top contains all |
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// logic necessery for debugging. |
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// |
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// Revision 1.1 2002/03/08 15:28:16 mohor |
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// Structure changed. Hooks for jtag chain added. |
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// |
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// |
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// |
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// |
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// Top module |
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module tap_top #(parameter |
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// 0001 version |
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// 0100100101010001 part number (IQ) |
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// 00011100001 manufacturer id (flextronics) |
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// 1 required by standard |
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IDCODE_VALUE = 32'h149511c3, |
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IR_LENGTH = 4) |
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( |
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// JTAG pads |
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tms_pad_i, |
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tck_pad_i, |
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trst_pad_i, |
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tdi_pad_i, |
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tdo_pad_o, |
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tdo_padoe_o, |
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|
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// TAP states |
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shift_dr_o, |
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pause_dr_o, |
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update_dr_o, |
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capture_dr_o, |
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|
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// Select signals for boundary scan or mbist |
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extest_select_o, |
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sample_preload_select_o, |
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mbist_select_o, |
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debug_select_o, |
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// TDO signal that is connected to TDI of sub-modules. |
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tdo_o, |
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// TDI signals from sub-modules |
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debug_tdi_i, // from debug module |
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bs_chain_tdi_i, // from Boundary Scan Chain |
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mbist_tdi_i // from Mbist Chain |
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); |
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|
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// JTAG pins |
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input tms_pad_i; // JTAG test mode select pad |
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input tck_pad_i; // JTAG test clock pad |
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input trst_pad_i; // JTAG test reset pad |
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input tdi_pad_i; // JTAG test data input pad |
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output tdo_pad_o; // JTAG test data output pad |
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output tdo_padoe_o; // Output enable for JTAG test data output pad |
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// TAP states |
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output shift_dr_o; |
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output pause_dr_o; |
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output update_dr_o; |
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output capture_dr_o; |
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// Select signals for boundary scan or mbist |
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output extest_select_o; |
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output sample_preload_select_o; |
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output mbist_select_o; |
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output debug_select_o; |
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// TDO signal that is connected to TDI of sub-modules. |
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output tdo_o; |
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// TDI signals from sub-modules |
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input debug_tdi_i; // from debug module |
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input bs_chain_tdi_i; // from Boundary Scan Chain |
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input mbist_tdi_i; // from Mbist Chain |
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//Internal constants |
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localparam EXTEST = 4'b0000; |
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localparam SAMPLE_PRELOAD = 4'b0001; |
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localparam IDCODE = 4'b0010; |
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localparam DEBUG = 4'b1000; |
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localparam MBIST = 4'b1001; |
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localparam BYPASS = 4'b1111; |
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// Registers |
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reg test_logic_reset; |
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reg run_test_idle; |
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reg select_dr_scan; |
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reg capture_dr; |
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reg shift_dr; |
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reg exit1_dr; |
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reg pause_dr; |
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reg exit2_dr; |
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reg update_dr; |
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reg select_ir_scan; |
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reg capture_ir; |
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reg shift_ir, shift_ir_neg; |
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reg exit1_ir; |
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reg pause_ir; |
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reg exit2_ir; |
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reg update_ir; |
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reg extest_select; |
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reg sample_preload_select; |
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reg idcode_select; |
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reg mbist_select; |
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reg debug_select; |
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reg bypass_select; |
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reg tdo_pad_o; |
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reg tdo_padoe_o; |
||||
reg tms_q1, tms_q2, tms_q3, tms_q4; |
||||
wire tms_reset; |
||||
|
||||
assign tdo_o = tdi_pad_i; |
||||
assign shift_dr_o = shift_dr; |
||||
assign pause_dr_o = pause_dr; |
||||
assign update_dr_o = update_dr; |
||||
assign capture_dr_o = capture_dr; |
||||
|
||||
assign extest_select_o = extest_select; |
||||
assign sample_preload_select_o = sample_preload_select; |
||||
assign mbist_select_o = mbist_select; |
||||
assign debug_select_o = debug_select; |
||||
|
||||
|
||||
always @ (posedge tck_pad_i) |
||||
begin |
||||
tms_q1 <= tms_pad_i; |
||||
tms_q2 <= tms_q1; |
||||
tms_q3 <= tms_q2; |
||||
tms_q4 <= tms_q3; |
||||
end |
||||
|
||||
|
||||
assign tms_reset = tms_q1 & tms_q2 & tms_q3 & tms_q4 & tms_pad_i; // 5 consecutive TMS=1 causes reset |
||||
|
||||
|
||||
/********************************************************************************** |
||||
* * |
||||
* TAP State Machine: Fully JTAG compliant * |
||||
* * |
||||
**********************************************************************************/ |
||||
|
||||
// test_logic_reset state |
||||
always @ (posedge tck_pad_i or posedge trst_pad_i) |
||||
begin |
||||
if(trst_pad_i) |
||||
test_logic_reset<= 1'b1; |
||||
else if (tms_reset) |
||||
test_logic_reset<= 1'b1; |
||||
else |
||||
begin |
||||
if(tms_pad_i & (test_logic_reset | select_ir_scan)) |
||||
test_logic_reset<= 1'b1; |
||||
else |
||||
test_logic_reset<= 1'b0; |
||||
end |
||||
end |
||||
|
||||
// run_test_idle state |
||||
always @ (posedge tck_pad_i or posedge trst_pad_i) |
||||
begin |
||||
if(trst_pad_i) |
||||
run_test_idle<= 1'b0; |
||||
else if (tms_reset) |
||||
run_test_idle<= 1'b0; |
||||
else |
||||
if(~tms_pad_i & (test_logic_reset | run_test_idle | update_dr | update_ir)) |
||||
run_test_idle<= 1'b1; |
||||
else |
||||
run_test_idle<= 1'b0; |
||||
end |
||||
|
||||
// select_dr_scan state |
||||
always @ (posedge tck_pad_i or posedge trst_pad_i) |
||||
begin |
||||
if(trst_pad_i) |
||||
select_dr_scan<= 1'b0; |
||||
else if (tms_reset) |
||||
select_dr_scan<= 1'b0; |
||||
else |
||||
if(tms_pad_i & (run_test_idle | update_dr | update_ir)) |
||||
select_dr_scan<= 1'b1; |
||||
else |
||||
select_dr_scan<= 1'b0; |
||||
end |
||||
|
||||
// capture_dr state |
||||
always @ (posedge tck_pad_i or posedge trst_pad_i) |
||||
begin |
||||
if(trst_pad_i) |
||||
capture_dr<= 1'b0; |
||||
else if (tms_reset) |
||||
capture_dr<= 1'b0; |
||||
else |
||||
if(~tms_pad_i & select_dr_scan) |
||||
capture_dr<= 1'b1; |
||||
else |
||||
capture_dr<= 1'b0; |
||||
end |
||||
|
||||
// shift_dr state |
||||
always @ (posedge tck_pad_i or posedge trst_pad_i) |
||||
begin |
||||
if(trst_pad_i) |
||||
shift_dr<= 1'b0; |
||||
else if (tms_reset) |
||||
shift_dr<= 1'b0; |
||||
else |
||||
if(~tms_pad_i & (capture_dr | shift_dr | exit2_dr)) |
||||
shift_dr<= 1'b1; |
||||
else |
||||
shift_dr<= 1'b0; |
||||
end |
||||
|
||||
// exit1_dr state |
||||
always @ (posedge tck_pad_i or posedge trst_pad_i) |
||||
begin |
||||
if(trst_pad_i) |
||||
exit1_dr<= 1'b0; |
||||
else if (tms_reset) |
||||
exit1_dr<= 1'b0; |
||||
else |
||||
if(tms_pad_i & (capture_dr | shift_dr)) |
||||
exit1_dr<= 1'b1; |
||||
else |
||||
exit1_dr<= 1'b0; |
||||
end |
||||
|
||||
// pause_dr state |
||||
always @ (posedge tck_pad_i or posedge trst_pad_i) |
||||
begin |
||||
if(trst_pad_i) |
||||
pause_dr<= 1'b0; |
||||
else if (tms_reset) |
||||
pause_dr<= 1'b0; |
||||
else |
||||
if(~tms_pad_i & (exit1_dr | pause_dr)) |
||||
pause_dr<= 1'b1; |
||||
else |
||||
pause_dr<= 1'b0; |
||||
end |
||||
|
||||
// exit2_dr state |
||||
always @ (posedge tck_pad_i or posedge trst_pad_i) |
||||
begin |
||||
if(trst_pad_i) |
||||
exit2_dr<= 1'b0; |
||||
else if (tms_reset) |
||||
exit2_dr<= 1'b0; |
||||
else |
||||
if(tms_pad_i & pause_dr) |
||||
exit2_dr<= 1'b1; |
||||
else |
||||
exit2_dr<= 1'b0; |
||||
end |
||||
|
||||
// update_dr state |
||||
always @ (posedge tck_pad_i or posedge trst_pad_i) |
||||
begin |
||||
if(trst_pad_i) |
||||
update_dr<= 1'b0; |
||||
else if (tms_reset) |
||||
update_dr<= 1'b0; |
||||
else |
||||
if(tms_pad_i & (exit1_dr | exit2_dr)) |
||||
update_dr<= 1'b1; |
||||
else |
||||
update_dr<= 1'b0; |
||||
end |
||||
|
||||
// select_ir_scan state |
||||
always @ (posedge tck_pad_i or posedge trst_pad_i) |
||||
begin |
||||
if(trst_pad_i) |
||||
select_ir_scan<= 1'b0; |
||||
else if (tms_reset) |
||||
select_ir_scan<= 1'b0; |
||||
else |
||||
if(tms_pad_i & select_dr_scan) |
||||
select_ir_scan<= 1'b1; |
||||
else |
||||
select_ir_scan<= 1'b0; |
||||
end |
||||
|
||||
// capture_ir state |
||||
always @ (posedge tck_pad_i or posedge trst_pad_i) |
||||
begin |
||||
if(trst_pad_i) |
||||
capture_ir<= 1'b0; |
||||
else if (tms_reset) |
||||
capture_ir<= 1'b0; |
||||
else |
||||
if(~tms_pad_i & select_ir_scan) |
||||
capture_ir<= 1'b1; |
||||
else |
||||
capture_ir<= 1'b0; |
||||
end |
||||
|
||||
// shift_ir state |
||||
always @ (posedge tck_pad_i or posedge trst_pad_i) |
||||
begin |
||||
if(trst_pad_i) |
||||
shift_ir<= 1'b0; |
||||
else if (tms_reset) |
||||
shift_ir<= 1'b0; |
||||
else |
||||
if(~tms_pad_i & (capture_ir | shift_ir | exit2_ir)) |
||||
shift_ir<= 1'b1; |
||||
else |
||||
shift_ir<= 1'b0; |
||||
end |
||||
|
||||
// exit1_ir state |
||||
always @ (posedge tck_pad_i or posedge trst_pad_i) |
||||
begin |
||||
if(trst_pad_i) |
||||
exit1_ir<= 1'b0; |
||||
else if (tms_reset) |
||||
exit1_ir<= 1'b0; |
||||
else |
||||
if(tms_pad_i & (capture_ir | shift_ir)) |
||||
exit1_ir<= 1'b1; |
||||
else |
||||
exit1_ir<= 1'b0; |
||||
end |
||||
|
||||
// pause_ir state |
||||
always @ (posedge tck_pad_i or posedge trst_pad_i) |
||||
begin |
||||
if(trst_pad_i) |
||||
pause_ir<= 1'b0; |
||||
else if (tms_reset) |
||||
pause_ir<= 1'b0; |
||||
else |
||||
if(~tms_pad_i & (exit1_ir | pause_ir)) |
||||
pause_ir<= 1'b1; |
||||
else |
||||
pause_ir<= 1'b0; |
||||
end |
||||
|
||||
// exit2_ir state |
||||
always @ (posedge tck_pad_i or posedge trst_pad_i) |
||||
begin |
||||
if(trst_pad_i) |
||||
exit2_ir<= 1'b0; |
||||
else if (tms_reset) |
||||
exit2_ir<= 1'b0; |
||||
else |
||||
if(tms_pad_i & pause_ir) |
||||
exit2_ir<= 1'b1; |
||||
else |
||||
exit2_ir<= 1'b0; |
||||
end |
||||
|
||||
// update_ir state |
||||
always @ (posedge tck_pad_i or posedge trst_pad_i) |
||||
begin |
||||
if(trst_pad_i) |
||||
update_ir<= 1'b0; |
||||
else if (tms_reset) |
||||
update_ir<= 1'b0; |
||||
else |
||||
if(tms_pad_i & (exit1_ir | exit2_ir)) |
||||
update_ir<= 1'b1; |
||||
else |
||||
update_ir<= 1'b0; |
||||
end |
||||
|
||||
/********************************************************************************** |
||||
* * |
||||
* End: TAP State Machine * |
||||
* * |
||||
**********************************************************************************/ |
||||
|
||||
|
||||
|
||||
/********************************************************************************** |
||||
* * |
||||
* jtag_ir: JTAG Instruction Register * |
||||
* * |
||||
**********************************************************************************/ |
||||
reg [IR_LENGTH-1:0] jtag_ir; // Instruction register |
||||
reg [IR_LENGTH-1:0] latched_jtag_ir, latched_jtag_ir_neg; |
||||
reg instruction_tdo; |
||||
|
||||
always @ (posedge tck_pad_i or posedge trst_pad_i) |
||||
begin |
||||
if(trst_pad_i) |
||||
jtag_ir[IR_LENGTH-1:0] <= {IR_LENGTH{1'b0}}; |
||||
else if(capture_ir) |
||||
jtag_ir <= 4'b0101; // This value is fixed for easier fault detection |
||||
else if(shift_ir) |
||||
jtag_ir[IR_LENGTH-1:0] <= {tdi_pad_i, jtag_ir[IR_LENGTH-1:1]}; |
||||
end |
||||
|
||||
always @ (negedge tck_pad_i) |
||||
begin |
||||
instruction_tdo <= jtag_ir[0]; |
||||
end |
||||
/********************************************************************************** |
||||
* * |
||||
* End: jtag_ir * |
||||
* * |
||||
**********************************************************************************/ |
||||
|
||||
|
||||
|
||||
/********************************************************************************** |
||||
* * |
||||
* idcode logic * |
||||
* * |
||||
**********************************************************************************/ |
||||
reg [31:0] idcode_reg; |
||||
reg idcode_tdo; |
||||
|
||||
always @ (posedge tck_pad_i) |
||||
begin |
||||
if(idcode_select & shift_dr) |
||||
idcode_reg <= {tdi_pad_i, idcode_reg[31:1]}; |
||||
else |
||||
idcode_reg <= IDCODE_VALUE; |
||||
end |
||||
|
||||
always @ (negedge tck_pad_i) |
||||
begin |
||||
idcode_tdo <= idcode_reg[0]; |
||||
end |
||||
/********************************************************************************** |
||||
* * |
||||
* End: idcode logic * |
||||
* * |
||||
**********************************************************************************/ |
||||
|
||||
|
||||
/********************************************************************************** |
||||
* * |
||||
* Bypass logic * |
||||
* * |
||||
**********************************************************************************/ |
||||
reg bypassed_tdo; |
||||
reg bypass_reg; |
||||
|
||||
always @ (posedge tck_pad_i or posedge trst_pad_i) |
||||
begin |
||||
if (trst_pad_i) |
||||
bypass_reg<= 1'b0; |
||||
else if(shift_dr) |
||||
bypass_reg<= tdi_pad_i; |
||||
end |
||||
|
||||
always @ (negedge tck_pad_i) |
||||
begin |
||||
bypassed_tdo <= bypass_reg; |
||||
end |
||||
/********************************************************************************** |
||||
* * |
||||
* End: Bypass logic * |
||||
* * |
||||
**********************************************************************************/ |
||||
|
||||
|
||||
/********************************************************************************** |
||||
* * |
||||
* Activating Instructions * |
||||
* * |
||||
**********************************************************************************/ |
||||
// Updating jtag_ir (Instruction Register) |
||||
always @ (posedge tck_pad_i or posedge trst_pad_i) |
||||
begin |
||||
if(trst_pad_i) |
||||
latched_jtag_ir <= IDCODE; // IDCODE selected after reset |
||||
else if (tms_reset) |
||||
latched_jtag_ir <= IDCODE; // IDCODE selected after reset |
||||
else if(update_ir) |
||||
latched_jtag_ir <= jtag_ir; |
||||
end |
||||
|
||||
/********************************************************************************** |
||||
* * |
||||
* End: Activating Instructions * |
||||
* * |
||||
**********************************************************************************/ |
||||
|
||||
|
||||
// Updating jtag_ir (Instruction Register) |
||||
always @ (latched_jtag_ir) |
||||
begin |
||||
extest_select = 1'b0; |
||||
sample_preload_select = 1'b0; |
||||
idcode_select = 1'b0; |
||||
mbist_select = 1'b0; |
||||
debug_select = 1'b0; |
||||
bypass_select = 1'b0; |
||||
|
||||
case(latched_jtag_ir) /* synthesis parallel_case */ |
||||
EXTEST: extest_select = 1'b1; // External test |
||||
SAMPLE_PRELOAD: sample_preload_select = 1'b1; // Sample preload |
||||
IDCODE: idcode_select = 1'b1; // ID Code |
||||
MBIST: mbist_select = 1'b1; // Mbist test |
||||
DEBUG: debug_select = 1'b1; // Debug |
||||
BYPASS: bypass_select = 1'b1; // BYPASS |
||||
default: bypass_select = 1'b1; // BYPASS |
||||
endcase |
||||
end |
||||
|
||||
|
||||
|
||||
/********************************************************************************** |
||||
* * |
||||
* Multiplexing TDO data * |
||||
* * |
||||
**********************************************************************************/ |
||||
always @ (shift_ir_neg or exit1_ir or instruction_tdo or latched_jtag_ir_neg or idcode_tdo or |
||||
debug_tdi_i or bs_chain_tdi_i or mbist_tdi_i or |
||||
bypassed_tdo) |
||||
begin |
||||
if(shift_ir_neg) |
||||
tdo_pad_o = instruction_tdo; |
||||
else |
||||
begin |
||||
case(latched_jtag_ir_neg) // synthesis parallel_case |
||||
IDCODE: tdo_pad_o = idcode_tdo; // Reading ID code |
||||
DEBUG: tdo_pad_o = debug_tdi_i; // Debug |
||||
SAMPLE_PRELOAD: tdo_pad_o = bs_chain_tdi_i; // Sampling/Preloading |
||||
EXTEST: tdo_pad_o = bs_chain_tdi_i; // External test |
||||
MBIST: tdo_pad_o = mbist_tdi_i; // Mbist test |
||||
default: tdo_pad_o = bypassed_tdo; // BYPASS instruction |
||||
endcase |
||||
end |
||||
end |
||||
|
||||
|
||||
// Tristate control for tdo_pad_o pin |
||||
always @ (negedge tck_pad_i) |
||||
begin |
||||
tdo_padoe_o <= shift_ir | shift_dr | (pause_dr & debug_select); |
||||
end |
||||
/********************************************************************************** |
||||
* * |
||||
* End: Multiplexing TDO data * |
||||
* * |
||||
**********************************************************************************/ |
||||
|
||||
|
||||
always @ (negedge tck_pad_i) |
||||
begin |
||||
shift_ir_neg <= shift_ir; |
||||
latched_jtag_ir_neg <= latched_jtag_ir; |
||||
end |
||||
|
||||
|
||||
endmodule |
@ -0,0 +1,196 @@
@@ -0,0 +1,196 @@
|
||||
#include <stdint.h> |
||||
#include <stdio.h> |
||||
#include <stdlib.h> |
||||
#include <string.h> |
||||
#include <unistd.h> |
||||
#include <poll.h> |
||||
#include <signal.h> |
||||
#include <fcntl.h> |
||||
#include <stdint.h> |
||||
#include <sys/types.h> |
||||
#include <sys/socket.h> |
||||
#include <netinet/in.h> |
||||
|
||||
#undef DEBUG |
||||
|
||||
/* XXX Make that some parameter */ |
||||
#define TCP_PORT 13245 |
||||
|
||||
static int fd = -1; |
||||
static int cfd = -1; |
||||
|
||||
static void open_socket(void) |
||||
{ |
||||
struct sockaddr_in addr; |
||||
int opt, rc, flags; |
||||
|
||||
if (fd >= 0 || fd < -1) |
||||
return; |
||||
|
||||
signal(SIGPIPE, SIG_IGN); |
||||
fd = socket(AF_INET, SOCK_STREAM, 0); |
||||
if (fd < 0) { |
||||
fprintf(stderr, "Failed to open debug socket\r\n"); |
||||
goto fail; |
||||
} |
||||
|
||||
rc = 0; |
||||
flags = fcntl(fd, F_GETFL); |
||||
if (flags >= 0) |
||||
rc = fcntl(fd, F_SETFL, flags | O_NONBLOCK); |
||||
if (flags < 0 || rc < 0) { |
||||
fprintf(stderr, "Failed to configure debug socket\r\n"); |
||||
} |
||||
|
||||
memset(&addr, 0, sizeof(addr)); |
||||
addr.sin_family = AF_INET; |
||||
addr.sin_port = htons(TCP_PORT); |
||||
addr.sin_addr.s_addr = htonl(INADDR_ANY); |
||||
opt = 1; |
||||
setsockopt(fd, SOL_SOCKET, SO_REUSEADDR, &opt, sizeof(opt)); |
||||
rc = bind(fd, (struct sockaddr *)&addr, sizeof(addr)); |
||||
if (rc < 0) { |
||||
fprintf(stderr, "Failed to bind debug socket\r\n"); |
||||
goto fail; |
||||
} |
||||
rc = listen(fd,1); |
||||
if (rc < 0) { |
||||
fprintf(stderr, "Failed to listen to debug socket\r\n"); |
||||
goto fail; |
||||
} |
||||
#ifdef DEBUG |
||||
fprintf(stdout, "Debug socket ready\r\n"); |
||||
#endif |
||||
return; |
||||
fail: |
||||
if (fd >= 0) |
||||
close(fd); |
||||
fd = -2; |
||||
} |
||||
|
||||
static void check_connection(void) |
||||
{ |
||||
struct sockaddr_in addr; |
||||
socklen_t addr_len = sizeof(addr); |
||||
|
||||
cfd = accept(fd, (struct sockaddr *)&addr, &addr_len); |
||||
if (cfd < 0) |
||||
return; |
||||
#ifdef DEBUG |
||||
fprintf(stdout, "Debug client connected\r\n"); |
||||
#endif |
||||
} |
||||
|
||||
static bool read_one_byte(char *c) |
||||
{ |
||||
struct pollfd fdset[1]; |
||||
int rc; |
||||
|
||||
if (fd == -1) |
||||
open_socket(); |
||||
if (fd < 0) |
||||
return false; |
||||
if (cfd < 0) |
||||
check_connection(); |
||||
if (cfd < 0) |
||||
return false; |
||||
|
||||
memset(fdset, 0, sizeof(fdset)); |
||||
fdset[0].fd = cfd; |
||||
fdset[0].events = POLLIN; |
||||
rc = poll(fdset, 1, 0); |
||||
if (rc <= 0) |
||||
return false; |
||||
rc = read(cfd, c, 1); |
||||
if (rc != 1) { |
||||
#ifdef DEBUG |
||||
fprintf(stdout, "Debug read error, assuming client disconnected !\r\n"); |
||||
#endif |
||||
close(cfd); |
||||
cfd = -1; |
||||
return false; |
||||
} |
||||
|
||||
#ifdef DEBUG |
||||
fprintf(stdout, "Got message: %c\n", *c); |
||||
#endif |
||||
|
||||
return true; |
||||
} |
||||
|
||||
static void write_one_byte(char c) |
||||
{ |
||||
int rc; |
||||
|
||||
#ifdef DEBUG |
||||
fprintf(stdout, "Sending message: %c\r\n", c); |
||||
#endif |
||||
|
||||
rc = write(cfd, &c, 1); |
||||
if (rc != 1) { |
||||
#ifdef DEBUG |
||||
fprintf(stdout, "JTAG write error, disconnecting\r\n"); |
||||
#endif |
||||
close(cfd); |
||||
cfd = -1; |
||||
} |
||||
} |
||||
|
||||
struct jtag_in { |
||||
uint8_t tck; |
||||
uint8_t tms; |
||||
uint8_t tdi; |
||||
uint8_t trst; |
||||
}; |
||||
|
||||
static struct jtag_in jtag_in; |
||||
|
||||
struct jtag_in jtag_one_cycle(uint8_t tdo) |
||||
{ |
||||
char c; |
||||
|
||||
if (read_one_byte(&c) == false) |
||||
goto out; |
||||
|
||||
// Write request |
||||
if ((c >= '0') && (c <= '7')) { |
||||
uint8_t val = c - '0'; |
||||
|
||||
jtag_in.tck = (val >> 2) & 1; |
||||
jtag_in.tms = (val >> 1) & 1; |
||||
jtag_in.tdi = (val >> 0) & 1; |
||||
|
||||
goto out; |
||||
} |
||||
|
||||
// Reset request |
||||
if ((c >= 'r') && (c <= 'u')) { |
||||
uint8_t val = c - 'r'; |
||||
|
||||
jtag_in.trst = (val >> 1) & 1; |
||||
} |
||||
|
||||
switch (c) { |
||||
case 'B': // Blink on |
||||
case 'b': // Blink off |
||||
goto out; |
||||
|
||||
case 'R': // Read request |
||||
write_one_byte(tdo + '0'); |
||||
goto out; |
||||
|
||||
case 'Q': // Quit request |
||||
#ifdef DEBUG |
||||
fprintf(stdout, "Disconnecting JTAG\r\n"); |
||||
#endif |
||||
close(cfd); |
||||
cfd = -1; |
||||
goto out; |
||||
|
||||
default: |
||||
fprintf(stderr, "Unknown JTAG command %c\r\n", c); |
||||
} |
||||
|
||||
out: |
||||
return jtag_in; |
||||
} |
Loading…
Reference in new issue