forked from cores/microwatt
2 changed files with 124 additions and 0 deletions
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#!/usr/bin/python |
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import sys |
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import re |
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module_regex = r'[a-zA-Z0-9_\.\\]+' |
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# match: |
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# module dcache(clk, rst, d_in, m_in, wishbone_in, d_out, m_out, stall_out, wishbone_out); |
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module_re = re.compile(r'module\s+(' + module_regex + r')\((.*)\);') |
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# match: |
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# dcache_64_2_2_2_2_12_0 dcache_0 ( |
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hookup_re = re.compile(r'\s+(' + module_regex + r') ' + module_regex + r'\s+\(') |
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header1 = """\ |
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`ifdef USE_POWER_PINS |
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vdda1, vdda2, vssa1, vssa2, vccd1, vccd2, vssd1, vssd2, |
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`endif\ |
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""" |
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header2 = """\ |
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`ifdef USE_POWER_PINS |
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inout vdda1; // User area 1 3.3V supply |
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inout vdda2; // User area 2 3.3V supply |
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inout vssa1; // User area 1 analog ground |
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inout vssa2; // User area 2 analog ground |
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inout vccd1; // User area 1 1.8V supply |
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inout vccd2; // User area 2 1.8v supply |
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inout vssd1; // User area 1 digital ground |
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inout vssd2; // User area 2 digital ground |
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`endif\ |
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""" |
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header3 = """\ |
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`ifdef USE_POWER_PINS |
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.vdda1(vdda1), // User area 1 3.3V power |
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.vdda2(vdda2), // User area 2 3.3V power |
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.vssa1(vssa1), // User area 1 analog ground |
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.vssa2(vssa2), // User area 2 analog ground |
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.vccd1(vccd1), // User area 1 1.8V power |
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.vccd2(vccd2), // User area 2 1.8V power |
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.vssd1(vssd1), // User area 1 digital ground |
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.vssd2(vssd2), // User area 2 digital ground |
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`endif\ |
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""" |
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if len(sys.argv) < 3: |
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print("Usage: insert_power.py verilog.v module1 module2..") |
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sys.exit(1); |
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verilog_file = sys.argv[1] |
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modules = sys.argv[2:] |
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with open(sys.argv[1]) as f: |
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for line in f: |
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m = module_re.match(line) |
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m2 = hookup_re.match(line) |
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if m and m.group(1) in modules: |
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module_name = m.group(1) |
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module_args = m.group(2) |
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print('module %s(' % module_name) |
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print(header1) |
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print(' %s);' % module_args) |
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print(header2) |
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elif m2 and m2.group(1) in modules: |
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print(line, end='') |
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print(header3) |
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else: |
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print(line, end='') |
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#!/bin/bash -e |
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# process microwatt verilog |
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FILE=microwatt.v |
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# Remove these modules that are implemented as hard macros |
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for module in register_file_0_1489f923c4dca729178b3e3233458550d8dddf29 dcache_64_2_2_2_2_12_0 icache_64_8_2_2_4_12_56_0_5ba93c9db0cff93f52b521d7420e43f6eda2784f cache_ram_4_64_1489f923c4dca729178b3e3233458550d8dddf29 cache_ram_4_64_3f29546453678b855931c174a97d6c0894b8f546 plru_1 multiply_4 |
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do |
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sed -i "/^module $module/,/^endmodule/d" $FILE |
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done |
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# Remove the debug bus in the places we call our macros |
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for module in dcache_64_2_2_2_2_12_0 icache_64_8_2_2_4_12_56_0_5ba93c9db0cff93f52b521d7420e43f6eda2784f register_file_0_1489f923c4dca729178b3e3233458550d8dddf29; do |
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for port in dbg_gpr log_out sim_dump; do |
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sed -i "/ $module /,/);/{ /$port/d }" $FILE |
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done |
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done |
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# Rename these modules to match the hard macro names |
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sed -i 's/register_file_0_1489f923c4dca729178b3e3233458550d8dddf29/register_file/' $FILE |
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sed -i 's/dcache_64_2_2_2_2_12_0/dcache/' $FILE |
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sed -i 's/icache_64_8_2_2_4_12_56_0_5ba93c9db0cff93f52b521d7420e43f6eda2784f/icache/' $FILE |
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sed -i 's/toplevel/microwatt/' $FILE |
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# Add power to all macros, and route power in microwatt down to them |
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caravel/insert_power.py $FILE dcache icache register_file multiply_4 RAM_512x64 main_bram_64_10_4096_a75adb9e07879fb6c63b494abe06e3f9a6bb2ed9 soc_4096_50000000_0_0_4_0_4_0_c832069ef22b63469d396707bc38511cc2410ddb wishbone_bram_wrapper_4096_a75adb9e07879fb6c63b494abe06e3f9a6bb2ed9 microwatt core_0_602f7ae323a872754ff5ac989c2e00f60e206d8e execute1_0_0e356ba505631fbf715758bed27d503f8b260e3a > $FILE.tmp && mv $FILE.tmp $FILE |
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# Add defines |
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sed -i '1 a\ |
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\ |
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/* Hard macros */\ |
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`ifdef SIM\ |
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`include "RAM_512x64.v"\ |
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`include "register_file.v"\ |
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`include "icache.v"\ |
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`include "dcache.v"\ |
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`include "multiply_4.v"\ |
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`endif\ |
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\ |
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/* JTAG */\ |
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`include "tap_top.v"\ |
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\ |
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/* UART */\ |
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`include "raminfr.v"\ |
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`include "uart_receiver.v"\ |
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`include "uart_rfifo.v"\ |
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`include "uart_tfifo.v"\ |
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`include "uart_transmitter.v"\ |
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`include "uart_defines.v"\ |
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`include "uart_regs.v"\ |
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`include "uart_sync_flops.v"\ |
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`include "uart_wb.v"\ |
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`include "uart_top.v"' $FILE |
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