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@ -79,32 +79,33 @@ architecture behaviour of decode2 is
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function decode_input_reg_b (t : input_reg_b_t; insn_in : std_ulogic_vector(31 downto 0);
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reg_data : std_ulogic_vector(63 downto 0);
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ispr : gspr_index_t) return decode_input_reg_t is
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variable ret : decode_input_reg_t;
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begin
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case t is
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when RB =>
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assert is_fast_spr(ispr) = '0' report "Decode B says GPR but ISPR says SPR:" &
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to_hstring(ispr) severity failure;
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return ('1', gpr_to_gspr(insn_rb(insn_in)), reg_data);
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ret := ('1', gpr_to_gspr(insn_rb(insn_in)), reg_data);
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when CONST_UI =>
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return ('0', (others => '0'), std_ulogic_vector(resize(unsigned(insn_ui(insn_in)), 64)));
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ret := ('0', (others => '0'), std_ulogic_vector(resize(unsigned(insn_ui(insn_in)), 64)));
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when CONST_SI =>
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return ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_si(insn_in)), 64)));
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ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_si(insn_in)), 64)));
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when CONST_SI_HI =>
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return ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_si(insn_in)) & x"0000", 64)));
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ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_si(insn_in)) & x"0000", 64)));
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when CONST_UI_HI =>
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return ('0', (others => '0'), std_ulogic_vector(resize(unsigned(insn_si(insn_in)) & x"0000", 64)));
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ret := ('0', (others => '0'), std_ulogic_vector(resize(unsigned(insn_si(insn_in)) & x"0000", 64)));
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when CONST_LI =>
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return ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_li(insn_in)) & "00", 64)));
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ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_li(insn_in)) & "00", 64)));
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when CONST_BD =>
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return ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_bd(insn_in)) & "00", 64)));
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ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_bd(insn_in)) & "00", 64)));
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when CONST_DS =>
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return ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_ds(insn_in)) & "00", 64)));
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ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_ds(insn_in)) & "00", 64)));
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when CONST_M1 =>
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return ('0', (others => '0'), x"FFFFFFFFFFFFFFFF");
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ret := ('0', (others => '0'), x"FFFFFFFFFFFFFFFF");
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when CONST_SH =>
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return ('0', (others => '0'), x"00000000000000" & "00" & insn_in(1) & insn_in(15 downto 11));
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ret := ('0', (others => '0'), x"00000000000000" & "00" & insn_in(1) & insn_in(15 downto 11));
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when CONST_SH32 =>
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return ('0', (others => '0'), x"00000000000000" & "000" & insn_in(15 downto 11));
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ret := ('0', (others => '0'), x"00000000000000" & "000" & insn_in(15 downto 11));
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when SPR =>
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-- ISPR must be either a valid fast SPR number or all 0 for a slow SPR.
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-- If it's all 0, we don't treat it as a dependency as slow SPRs
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@ -112,10 +113,12 @@ architecture behaviour of decode2 is
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assert is_fast_spr(ispr) = '1' or ispr = "000000"
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report "Decode B says SPR but ISPR is invalid:" &
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to_hstring(ispr) severity failure;
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return (is_fast_spr(ispr), ispr, reg_data);
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ret := (is_fast_spr(ispr), ispr, reg_data);
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when NONE =>
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return ('0', (others => '0'), (others => '0'));
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ret := ('0', (others => '0'), (others => '0'));
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end case;
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return ret;
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end;
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function decode_input_reg_c (t : input_reg_c_t; insn_in : std_ulogic_vector(31 downto 0);
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