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Add constraint file for Nexys A7

nia-debug
Olof Kindgren 4 years ago
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e8ad9bed10
commit
abca85b034
1 changed files with 7 additions and 0 deletions
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  1. 7
      fpga/nexys_a7.xdc

7
fpga/nexys_a7.xdc
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@ -0,0 +1,7 @@ @@ -0,0 +1,7 @@
set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS33} [get_ports clk]
create_clock -period 10.000 -name sys_clk_pin -waveform {0.000 5.000} -add [get_ports clk]

set_property -dict {PACKAGE_PIN C12 IOSTANDARD LVCMOS33} [get_ports reset_n]

set_property -dict {PACKAGE_PIN D4 IOSTANDARD LVCMOS33} [get_ports uart0_txd]
set_property -dict {PACKAGE_PIN C4 IOSTANDARD LVCMOS33} [get_ports uart0_rxd]
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