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@ -94,6 +94,10 @@ architecture behaviour of toplevel is
@@ -94,6 +94,10 @@ architecture behaviour of toplevel is
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signal spi_sdat_oe : std_ulogic_vector(3 downto 0); |
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signal spi_sdat_i : std_ulogic_vector(3 downto 0); |
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-- ddram clock signals as vectors |
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signal ddram_clk_p_vec : std_logic_vector(0 downto 0); |
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signal ddram_clk_n_vec : std_logic_vector(0 downto 0); |
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-- Fixup various memory sizes based on generics |
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function get_bram_size return natural is |
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begin |
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@ -252,6 +256,9 @@ begin
@@ -252,6 +256,9 @@ begin
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-- but for now, assert it's 100Mhz |
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assert CLK_FREQUENCY = 100000000; |
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ddram_clk_p_vec <= (others => ddram_clk_p); |
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ddram_clk_n_vec <= (others => ddram_clk_n); |
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reset_controller: entity work.soc_reset |
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generic map( |
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RESET_LOW => false, |
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@ -272,6 +279,7 @@ begin
@@ -272,6 +279,7 @@ begin
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DRAM_ABITS => 26, |
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DRAM_ALINES => 16, |
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DRAM_DLINES => 16, |
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DRAM_CKLINES => 1, |
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DRAM_PORT_WIDTH => 128, |
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PAYLOAD_FILE => RAM_INIT_FILE, |
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PAYLOAD_SIZE => PAYLOAD_SIZE |
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@ -304,8 +312,8 @@ begin
@@ -304,8 +312,8 @@ begin
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ddram_dq => ddram_dq, |
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ddram_dqs_p => ddram_dqs_p, |
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ddram_dqs_n => ddram_dqs_n, |
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ddram_clk_p => ddram_clk_p, |
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ddram_clk_n => ddram_clk_n, |
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ddram_clk_p => ddram_clk_p_vec, |
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ddram_clk_n => ddram_clk_n_vec, |
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ddram_cke => ddram_cke, |
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ddram_odt => ddram_odt, |
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ddram_reset_n => ddram_reset_n |
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