forked from cores/microwatt
Merge branch 'divider' of https://github.com/paulusmack/microwatt
Anton Blanchard
commit
b57325ce29
@ -0,0 +1,133 @@
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.common.all;
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use work.decode_types.all;
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use work.crhelpers.all;
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entity divider is
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port (
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clk : in std_logic;
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rst : in std_logic;
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d_in : in Decode2ToDividerType;
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d_out : out DividerToWritebackType
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);
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end entity divider;
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architecture behaviour of divider is
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signal dend : std_ulogic_vector(127 downto 0);
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signal div : unsigned(63 downto 0);
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signal quot : std_ulogic_vector(63 downto 0);
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signal result : std_ulogic_vector(63 downto 0);
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signal sresult : std_ulogic_vector(63 downto 0);
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signal qbit : std_ulogic;
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signal running : std_ulogic;
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signal count : unsigned(6 downto 0);
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signal neg_result : std_ulogic;
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signal is_modulus : std_ulogic;
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signal is_32bit : std_ulogic;
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signal rc : std_ulogic;
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signal write_reg : std_ulogic_vector(4 downto 0);
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function compare_zero(value : std_ulogic_vector(63 downto 0); is_32 : std_ulogic)
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return std_ulogic_vector is
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begin
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if is_32 = '1' then
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if value(31) = '1' then
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return "1000";
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elsif unsigned(value(30 downto 0)) > 0 then
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return "0100";
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else
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return "0010";
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end if;
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else
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if value(63) = '1' then
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return "1000";
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elsif unsigned(value(62 downto 0)) > 0 then
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return "0100";
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else
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return "0010";
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end if;
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end if;
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end function compare_zero;
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begin
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divider_0: process(clk)
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begin
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if rising_edge(clk) then
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if rst = '1' then
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dend <= (others => '0');
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div <= (others => '0');
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quot <= (others => '0');
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running <= '0';
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count <= "0000000";
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elsif d_in.valid = '1' then
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if d_in.is_extended = '1' then
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dend <= d_in.dividend & x"0000000000000000";
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else
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dend <= x"0000000000000000" & d_in.dividend;
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end if;
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div <= unsigned(d_in.divisor);
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quot <= (others => '0');
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write_reg <= d_in.write_reg;
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neg_result <= d_in.neg_result;
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is_modulus <= d_in.is_modulus;
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is_32bit <= d_in.is_32bit;
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rc <= d_in.rc;
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count <= "0000000";
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running <= '1';
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elsif running = '1' then
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if count = "0111111" then
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running <= '0';
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end if;
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if dend(127) = '1' or unsigned(dend(126 downto 63)) >= div then
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dend <= std_ulogic_vector(unsigned(dend(126 downto 63)) - div) &
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dend(62 downto 0) & '0';
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quot <= quot(62 downto 0) & '1';
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count <= count + 1;
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elsif dend(127 downto 56) = x"000000000000000000" and count(5 downto 3) /= "111" then
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-- consume 8 bits of zeroes in one cycle
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dend <= dend(119 downto 0) & x"00";
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quot <= quot(55 downto 0) & x"00";
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count <= count + 8;
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else
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dend <= dend(126 downto 0) & '0';
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quot <= quot(62 downto 0) & '0';
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count <= count + 1;
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end if;
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else
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count <= "0000000";
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end if;
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end if;
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end process;
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divider_1: process(all)
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begin
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d_out <= DividerToWritebackInit;
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d_out.write_reg_nr <= write_reg;
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if count(6) = '1' then
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d_out.valid <= '1';
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d_out.write_reg_enable <= '1';
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if is_modulus = '1' then
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result <= dend(127 downto 64);
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else
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result <= quot;
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end if;
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if neg_result = '1' then
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sresult <= std_ulogic_vector(- signed(result));
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else
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sresult <= result;
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end if;
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d_out.write_reg_data <= sresult;
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if rc = '1' then
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d_out.write_cr_enable <= '1';
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d_out.write_cr_mask <= num_to_fxm(0);
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d_out.write_cr_data <= compare_zero(sresult, is_32bit) & x"0000000";
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end if;
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end if;
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end process;
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end architecture behaviour;
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@ -0,0 +1,613 @@
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.decode_types.all;
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use work.common.all;
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use work.glibc_random.all;
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use work.ppc_fx_insns.all;
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entity divider_tb is
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end divider_tb;
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architecture behave of divider_tb is
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signal clk : std_ulogic;
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signal rst : std_ulogic;
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constant clk_period : time := 10 ns;
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signal d1 : Decode2ToDividerType;
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signal d2 : DividerToWritebackType;
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begin
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divider_0: entity work.divider
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port map (clk => clk, rst => rst, d_in => d1, d_out => d2);
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clk_process: process
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begin
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clk <= '0';
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wait for clk_period/2;
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clk <= '1';
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wait for clk_period/2;
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end process;
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stim_process: process
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variable ra, rb, rt, behave_rt: std_ulogic_vector(63 downto 0);
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variable si: std_ulogic_vector(15 downto 0);
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variable d128: std_ulogic_vector(127 downto 0);
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variable q128: std_ulogic_vector(127 downto 0);
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begin
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rst <= '1';
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wait for clk_period;
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rst <= '0';
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d1.valid <= '1';
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d1.write_reg <= "10001";
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d1.dividend <= x"0000000010001000";
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d1.divisor <= x"0000000000001111";
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d1.neg_result <= '0';
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d1.is_32bit <= '0';
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d1.is_extended <= '0';
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d1.is_modulus <= '0';
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d1.rc <= '0';
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wait for clk_period;
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assert d2.valid = '0';
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d1.valid <= '0';
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for j in 0 to 64 loop
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wait for clk_period;
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if d2.valid = '1' then
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exit;
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end if;
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end loop;
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assert d2.valid = '1';
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assert d2.write_reg_enable = '1';
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assert d2.write_reg_nr = "10001";
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assert d2.write_reg_data = x"000000000000f001" report "result " & to_hstring(d2.write_reg_data);
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assert d2.write_cr_enable = '0';
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wait for clk_period;
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assert d2.valid = '0' report "valid";
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d1.valid <= '1';
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d1.rc <= '1';
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wait for clk_period;
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assert d2.valid = '0' report "valid";
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d1.valid <= '0';
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for j in 0 to 64 loop
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wait for clk_period;
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if d2.valid = '1' then
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exit;
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end if;
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end loop;
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assert d2.valid = '1';
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assert d2.write_reg_enable = '1';
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assert d2.write_reg_nr = "10001";
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assert d2.write_reg_data = x"000000000000f001" report "result " & to_hstring(d2.write_reg_data);
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assert d2.write_cr_enable = '1';
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assert d2.write_cr_mask = "10000000";
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assert d2.write_cr_data = x"40000000" report "cr data is " & to_hstring(d2.write_cr_data);
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wait for clk_period;
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assert d2.valid = '0';
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-- test divd
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report "test divd";
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divd_loop : for dlength in 1 to 8 loop
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for vlength in 1 to dlength loop
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for i in 0 to 100 loop
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ra := std_ulogic_vector(resize(signed(pseudorand(dlength * 8)), 64));
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rb := std_ulogic_vector(resize(signed(pseudorand(vlength * 8)), 64));
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if ra(63) = '1' then
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d1.dividend <= std_ulogic_vector(- signed(ra));
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else
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d1.dividend <= ra;
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end if;
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if rb(63) = '1' then
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d1.divisor <= std_ulogic_vector(- signed(rb));
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else
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d1.divisor <= rb;
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end if;
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if ra(63) = rb(63) then
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d1.neg_result <= '0';
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else
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d1.neg_result <= '1';
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end if;
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d1.valid <= '1';
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wait for clk_period;
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d1.valid <= '0';
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for j in 0 to 64 loop
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wait for clk_period;
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if d2.valid = '1' then
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exit;
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end if;
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end loop;
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assert d2.valid = '1';
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if rb /= x"0000000000000000" then
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behave_rt := ppc_divd(ra, rb);
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assert to_hstring(behave_rt) = to_hstring(d2.write_reg_data)
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report "bad divd expected " & to_hstring(behave_rt) & " got " & to_hstring(d2.write_reg_data);
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assert ppc_cmpi('1', behave_rt, x"0000") & x"0000000" = d2.write_cr_data
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report "bad CR setting for divd";
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end if;
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end loop;
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end loop;
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end loop;
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-- test divdu
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report "test divdu";
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divdu_loop : for dlength in 1 to 8 loop
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for vlength in 1 to dlength loop
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for i in 0 to 100 loop
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ra := std_ulogic_vector(resize(unsigned(pseudorand(dlength * 8)), 64));
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rb := std_ulogic_vector(resize(unsigned(pseudorand(vlength * 8)), 64));
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d1.dividend <= ra;
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d1.divisor <= rb;
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d1.neg_result <= '0';
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d1.valid <= '1';
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wait for clk_period;
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d1.valid <= '0';
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for j in 0 to 64 loop
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wait for clk_period;
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if d2.valid = '1' then
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exit;
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end if;
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end loop;
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assert d2.valid = '1';
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if rb /= x"0000000000000000" then
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behave_rt := ppc_divdu(ra, rb);
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assert to_hstring(behave_rt) = to_hstring(d2.write_reg_data)
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report "bad divdu expected " & to_hstring(behave_rt) & " got " & to_hstring(d2.write_reg_data);
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assert ppc_cmpi('1', behave_rt, x"0000") & x"0000000" = d2.write_cr_data
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report "bad CR setting for divdu";
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end if;
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end loop;
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end loop;
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end loop;
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-- test divde
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report "test divde";
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divde_loop : for vlength in 1 to 8 loop
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for dlength in 1 to vlength loop
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for i in 0 to 100 loop
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ra := std_ulogic_vector(resize(signed(pseudorand(dlength * 8)), 64));
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rb := std_ulogic_vector(resize(signed(pseudorand(vlength * 8)), 64));
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if ra(63) = '1' then
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d1.dividend <= std_ulogic_vector(- signed(ra));
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else
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d1.dividend <= ra;
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end if;
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if rb(63) = '1' then
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d1.divisor <= std_ulogic_vector(- signed(rb));
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else
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d1.divisor <= rb;
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end if;
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if ra(63) = rb(63) then
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d1.neg_result <= '0';
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else
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d1.neg_result <= '1';
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end if;
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d1.is_extended <= '1';
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d1.valid <= '1';
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wait for clk_period;
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d1.valid <= '0';
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for j in 0 to 64 loop
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wait for clk_period;
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if d2.valid = '1' then
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exit;
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end if;
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end loop;
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assert d2.valid = '1';
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if unsigned(d1.divisor) > unsigned(d1.dividend) then
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d128 := ra & x"0000000000000000";
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q128 := std_ulogic_vector(signed(d128) / signed(rb));
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behave_rt := q128(63 downto 0);
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assert to_hstring(behave_rt) = to_hstring(d2.write_reg_data)
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report "bad divde expected " & to_hstring(behave_rt) & " got " & to_hstring(d2.write_reg_data) & " for ra = " & to_hstring(ra) & " rb = " & to_hstring(rb);
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assert ppc_cmpi('1', behave_rt, x"0000") & x"0000000" = d2.write_cr_data
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report "bad CR setting for divde";
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end if;
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end loop;
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end loop;
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end loop;
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-- test divdeu
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report "test divdeu";
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divdeu_loop : for vlength in 1 to 8 loop
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for dlength in 1 to vlength loop
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for i in 0 to 100 loop
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ra := std_ulogic_vector(resize(unsigned(pseudorand(dlength * 8)), 64));
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rb := std_ulogic_vector(resize(unsigned(pseudorand(vlength * 8)), 64));
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d1.dividend <= ra;
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d1.divisor <= rb;
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d1.neg_result <= '0';
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d1.is_extended <= '1';
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d1.valid <= '1';
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wait for clk_period;
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d1.valid <= '0';
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for j in 0 to 64 loop
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wait for clk_period;
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if d2.valid = '1' then
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exit;
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end if;
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end loop;
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assert d2.valid = '1';
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if unsigned(d1.divisor) > unsigned(d1.dividend) then
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d128 := ra & x"0000000000000000";
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q128 := std_ulogic_vector(unsigned(d128) / unsigned(rb));
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behave_rt := q128(63 downto 0);
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assert to_hstring(behave_rt) = to_hstring(d2.write_reg_data)
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report "bad divdeu expected " & to_hstring(behave_rt) & " got " & to_hstring(d2.write_reg_data) & " for ra = " & to_hstring(ra) & " rb = " & to_hstring(rb);
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assert ppc_cmpi('1', behave_rt, x"0000") & x"0000000" = d2.write_cr_data
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report "bad CR setting for divdeu";
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end if;
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end loop;
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end loop;
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end loop;
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-- test divw
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report "test divw";
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divw_loop : for dlength in 1 to 4 loop
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for vlength in 1 to dlength loop
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for i in 0 to 100 loop
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ra := std_ulogic_vector(resize(signed(pseudorand(dlength * 8)), 64));
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rb := std_ulogic_vector(resize(signed(pseudorand(vlength * 8)), 64));
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if ra(63) = '1' then
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d1.dividend <= std_ulogic_vector(- signed(ra));
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else
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d1.dividend <= ra;
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end if;
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if rb(63) = '1' then
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d1.divisor <= std_ulogic_vector(- signed(rb));
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else
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d1.divisor <= rb;
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end if;
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if ra(63) = rb(63) then
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d1.neg_result <= '0';
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else
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d1.neg_result <= '1';
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end if;
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d1.is_extended <= '0';
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d1.is_32bit <= '1';
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d1.valid <= '1';
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wait for clk_period;
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d1.valid <= '0';
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for j in 0 to 64 loop
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wait for clk_period;
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if d2.valid = '1' then
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exit;
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end if;
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end loop;
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assert d2.valid = '1';
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if rb /= x"0000000000000000" then
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behave_rt := ppc_divw(ra, rb);
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assert behave_rt(31 downto 0) = d2.write_reg_data(31 downto 0)
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report "bad divw expected " & to_hstring(behave_rt) & " got " & to_hstring(d2.write_reg_data);
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assert ppc_cmpi('0', behave_rt, x"0000") & x"0000000" = d2.write_cr_data
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report "bad CR setting for divw";
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end if;
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end loop;
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end loop;
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end loop;
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-- test divwu
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report "test divwu";
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divwu_loop : for dlength in 1 to 4 loop
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for vlength in 1 to dlength loop
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for i in 0 to 100 loop
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ra := std_ulogic_vector(resize(unsigned(pseudorand(dlength * 8)), 64));
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rb := std_ulogic_vector(resize(unsigned(pseudorand(vlength * 8)), 64));
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d1.dividend <= ra;
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d1.divisor <= rb;
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d1.neg_result <= '0';
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d1.is_extended <= '0';
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d1.is_32bit <= '1';
|
||||
d1.valid <= '1';
|
||||
|
||||
wait for clk_period;
|
||||
|
||||
d1.valid <= '0';
|
||||
for j in 0 to 64 loop
|
||||
wait for clk_period;
|
||||
if d2.valid = '1' then
|
||||
exit;
|
||||
end if;
|
||||
end loop;
|
||||
assert d2.valid = '1';
|
||||
|
||||
if rb /= x"0000000000000000" then
|
||||
behave_rt := ppc_divwu(ra, rb);
|
||||
assert behave_rt(31 downto 0) = d2.write_reg_data(31 downto 0)
|
||||
report "bad divwu expected " & to_hstring(behave_rt) & " got " & to_hstring(d2.write_reg_data);
|
||||
assert ppc_cmpi('0', behave_rt, x"0000") & x"0000000" = d2.write_cr_data
|
||||
report "bad CR setting for divwu";
|
||||
end if;
|
||||
end loop;
|
||||
end loop;
|
||||
end loop;
|
||||
|
||||
-- test divwe
|
||||
report "test divwe";
|
||||
divwe_loop : for vlength in 1 to 4 loop
|
||||
for dlength in 1 to vlength loop
|
||||
for i in 0 to 100 loop
|
||||
ra := std_ulogic_vector(resize(signed(pseudorand(dlength * 8)), 32)) & x"00000000";
|
||||
rb := std_ulogic_vector(resize(signed(pseudorand(vlength * 8)), 64));
|
||||
|
||||
if ra(63) = '1' then
|
||||
d1.dividend <= std_ulogic_vector(- signed(ra));
|
||||
else
|
||||
d1.dividend <= ra;
|
||||
end if;
|
||||
if rb(63) = '1' then
|
||||
d1.divisor <= std_ulogic_vector(- signed(rb));
|
||||
else
|
||||
d1.divisor <= rb;
|
||||
end if;
|
||||
if ra(63) = rb(63) then
|
||||
d1.neg_result <= '0';
|
||||
else
|
||||
d1.neg_result <= '1';
|
||||
end if;
|
||||
d1.is_extended <= '0';
|
||||
d1.is_32bit <= '1';
|
||||
d1.valid <= '1';
|
||||
|
||||
wait for clk_period;
|
||||
|
||||
d1.valid <= '0';
|
||||
for j in 0 to 64 loop
|
||||
wait for clk_period;
|
||||
if d2.valid = '1' then
|
||||
exit;
|
||||
end if;
|
||||
end loop;
|
||||
assert d2.valid = '1';
|
||||
|
||||
if unsigned(d1.divisor(31 downto 0)) > unsigned(d1.dividend(63 downto 32)) then
|
||||
behave_rt := std_ulogic_vector(signed(ra) / signed(rb));
|
||||
assert behave_rt(31 downto 0) = d2.write_reg_data(31 downto 0)
|
||||
report "bad divwe expected " & to_hstring(behave_rt) & " got " & to_hstring(d2.write_reg_data) & " for ra = " & to_hstring(ra) & " rb = " & to_hstring(rb);
|
||||
assert ppc_cmpi('0', behave_rt, x"0000") & x"0000000" = d2.write_cr_data
|
||||
report "bad CR setting for divwe";
|
||||
end if;
|
||||
end loop;
|
||||
end loop;
|
||||
end loop;
|
||||
|
||||
-- test divweu
|
||||
report "test divweu";
|
||||
divweu_loop : for vlength in 1 to 4 loop
|
||||
for dlength in 1 to vlength loop
|
||||
for i in 0 to 100 loop
|
||||
ra := std_ulogic_vector(resize(unsigned(pseudorand(dlength * 8)), 32)) & x"00000000";
|
||||
rb := std_ulogic_vector(resize(unsigned(pseudorand(vlength * 8)), 64));
|
||||
|
||||
d1.dividend <= ra;
|
||||
d1.divisor <= rb;
|
||||
d1.neg_result <= '0';
|
||||
d1.is_extended <= '0';
|
||||
d1.is_32bit <= '1';
|
||||
d1.valid <= '1';
|
||||
|
||||
wait for clk_period;
|
||||
|
||||
d1.valid <= '0';
|
||||
for j in 0 to 64 loop
|
||||
wait for clk_period;
|
||||
if d2.valid = '1' then
|
||||
exit;
|
||||
end if;
|
||||
end loop;
|
||||
assert d2.valid = '1';
|
||||
|
||||
if unsigned(d1.divisor(31 downto 0)) > unsigned(d1.dividend(63 downto 32)) then
|
||||
behave_rt := std_ulogic_vector(unsigned(ra) / unsigned(rb));
|
||||
assert behave_rt(31 downto 0) = d2.write_reg_data(31 downto 0)
|
||||
report "bad divweu expected " & to_hstring(behave_rt) & " got " & to_hstring(d2.write_reg_data) & " for ra = " & to_hstring(ra) & " rb = " & to_hstring(rb);
|
||||
assert ppc_cmpi('0', behave_rt, x"0000") & x"0000000" = d2.write_cr_data
|
||||
report "bad CR setting for divweu";
|
||||
end if;
|
||||
end loop;
|
||||
end loop;
|
||||
end loop;
|
||||
|
||||
-- test modsd
|
||||
report "test modsd";
|
||||
modsd_loop : for dlength in 1 to 8 loop
|
||||
for vlength in 1 to dlength loop
|
||||
for i in 0 to 100 loop
|
||||
ra := std_ulogic_vector(resize(signed(pseudorand(dlength * 8)), 64));
|
||||
rb := std_ulogic_vector(resize(signed(pseudorand(vlength * 8)), 64));
|
||||
|
||||
if ra(63) = '1' then
|
||||
d1.dividend <= std_ulogic_vector(- signed(ra));
|
||||
else
|
||||
d1.dividend <= ra;
|
||||
end if;
|
||||
if rb(63) = '1' then
|
||||
d1.divisor <= std_ulogic_vector(- signed(rb));
|
||||
else
|
||||
d1.divisor <= rb;
|
||||
end if;
|
||||
d1.neg_result <= ra(63);
|
||||
d1.is_extended <= '0';
|
||||
d1.is_32bit <= '0';
|
||||
d1.is_modulus <= '1';
|
||||
d1.valid <= '1';
|
||||
|
||||
wait for clk_period;
|
||||
|
||||
d1.valid <= '0';
|
||||
for j in 0 to 64 loop
|
||||
wait for clk_period;
|
||||
if d2.valid = '1' then
|
||||
exit;
|
||||
end if;
|
||||
end loop;
|
||||
assert d2.valid = '1';
|
||||
|
||||
if rb /= x"0000000000000000" then
|
||||
behave_rt := std_ulogic_vector(signed(ra) rem signed(rb));
|
||||
assert behave_rt = d2.write_reg_data
|
||||
report "bad modsd expected " & to_hstring(behave_rt) & " got " & to_hstring(d2.write_reg_data);
|
||||
assert ppc_cmpi('1', behave_rt, x"0000") & x"0000000" = d2.write_cr_data
|
||||
report "bad CR setting for modsd";
|
||||
end if;
|
||||
end loop;
|
||||
end loop;
|
||||
end loop;
|
||||
|
||||
-- test modud
|
||||
report "test modud";
|
||||
modud_loop : for dlength in 1 to 8 loop
|
||||
for vlength in 1 to dlength loop
|
||||
for i in 0 to 100 loop
|
||||
ra := std_ulogic_vector(resize(unsigned(pseudorand(dlength * 8)), 64));
|
||||
rb := std_ulogic_vector(resize(unsigned(pseudorand(vlength * 8)), 64));
|
||||
|
||||
d1.dividend <= ra;
|
||||
d1.divisor <= rb;
|
||||
d1.neg_result <= '0';
|
||||
d1.is_extended <= '0';
|
||||
d1.is_32bit <= '0';
|
||||
d1.is_modulus <= '1';
|
||||
d1.valid <= '1';
|
||||
|
||||
wait for clk_period;
|
||||
|
||||
d1.valid <= '0';
|
||||
for j in 0 to 64 loop
|
||||
wait for clk_period;
|
||||
if d2.valid = '1' then
|
||||
exit;
|
||||
end if;
|
||||
end loop;
|
||||
assert d2.valid = '1';
|
||||
|
||||
if rb /= x"0000000000000000" then
|
||||
behave_rt := std_ulogic_vector(unsigned(ra) rem unsigned(rb));
|
||||
assert behave_rt = d2.write_reg_data
|
||||
report "bad modud expected " & to_hstring(behave_rt) & " got " & to_hstring(d2.write_reg_data);
|
||||
assert ppc_cmpi('1', behave_rt, x"0000") & x"0000000" = d2.write_cr_data
|
||||
report "bad CR setting for modud";
|
||||
end if;
|
||||
end loop;
|
||||
end loop;
|
||||
end loop;
|
||||
|
||||
-- test modsw
|
||||
report "test modsw";
|
||||
modsw_loop : for dlength in 1 to 4 loop
|
||||
for vlength in 1 to dlength loop
|
||||
for i in 0 to 100 loop
|
||||
ra := std_ulogic_vector(resize(signed(pseudorand(dlength * 8)), 64));
|
||||
rb := std_ulogic_vector(resize(signed(pseudorand(vlength * 8)), 64));
|
||||
|
||||
if ra(63) = '1' then
|
||||
d1.dividend <= std_ulogic_vector(- signed(ra));
|
||||
else
|
||||
d1.dividend <= ra;
|
||||
end if;
|
||||
if rb(63) = '1' then
|
||||
d1.divisor <= std_ulogic_vector(- signed(rb));
|
||||
else
|
||||
d1.divisor <= rb;
|
||||
end if;
|
||||
d1.neg_result <= ra(63);
|
||||
d1.is_extended <= '0';
|
||||
d1.is_32bit <= '1';
|
||||
d1.is_modulus <= '1';
|
||||
d1.valid <= '1';
|
||||
|
||||
wait for clk_period;
|
||||
|
||||
d1.valid <= '0';
|
||||
for j in 0 to 64 loop
|
||||
wait for clk_period;
|
||||
if d2.valid = '1' then
|
||||
exit;
|
||||
end if;
|
||||
end loop;
|
||||
assert d2.valid = '1';
|
||||
|
||||
if rb /= x"0000000000000000" then
|
||||
behave_rt := x"00000000" & std_ulogic_vector(signed(ra(31 downto 0)) rem signed(rb(31 downto 0)));
|
||||
assert behave_rt(31 downto 0) = d2.write_reg_data(31 downto 0)
|
||||
report "bad modsw expected " & to_hstring(behave_rt) & " got " & to_hstring(d2.write_reg_data);
|
||||
assert ppc_cmpi('0', behave_rt, x"0000") & x"0000000" = d2.write_cr_data
|
||||
report "bad CR setting for modsw";
|
||||
end if;
|
||||
end loop;
|
||||
end loop;
|
||||
end loop;
|
||||
|
||||
-- test moduw
|
||||
report "test moduw";
|
||||
moduw_loop : for dlength in 1 to 4 loop
|
||||
for vlength in 1 to dlength loop
|
||||
for i in 0 to 100 loop
|
||||
ra := std_ulogic_vector(resize(unsigned(pseudorand(dlength * 8)), 64));
|
||||
rb := std_ulogic_vector(resize(unsigned(pseudorand(vlength * 8)), 64));
|
||||
|
||||
d1.dividend <= ra;
|
||||
d1.divisor <= rb;
|
||||
d1.neg_result <= '0';
|
||||
d1.is_extended <= '0';
|
||||
d1.is_32bit <= '1';
|
||||
d1.is_modulus <= '1';
|
||||
d1.valid <= '1';
|
||||
|
||||
wait for clk_period;
|
||||
|
||||
d1.valid <= '0';
|
||||
for j in 0 to 64 loop
|
||||
wait for clk_period;
|
||||
if d2.valid = '1' then
|
||||
exit;
|
||||
end if;
|
||||
end loop;
|
||||
assert d2.valid = '1';
|
||||
|
||||
if rb /= x"0000000000000000" then
|
||||
behave_rt := x"00000000" & std_ulogic_vector(unsigned(ra(31 downto 0)) rem unsigned(rb(31 downto 0)));
|
||||
assert behave_rt(31 downto 0) = d2.write_reg_data(31 downto 0)
|
||||
report "bad moduw expected " & to_hstring(behave_rt) & " got " & to_hstring(d2.write_reg_data);
|
||||
assert ppc_cmpi('0', behave_rt, x"0000") & x"0000000" = d2.write_cr_data
|
||||
report "bad CR setting for moduw";
|
||||
end if;
|
||||
end loop;
|
||||
end loop;
|
||||
end loop;
|
||||
|
||||
assert false report "end of test" severity failure;
|
||||
wait;
|
||||
end process;
|
||||
end behave;
|
||||
Loading…
Reference in New Issue