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@ -12,25 +12,25 @@ entity core_debug is
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LOG_LENGTH : natural := 512
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);
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port (
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clk : in std_logic;
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rst : in std_logic;
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dmi_addr : in std_ulogic_vector(3 downto 0);
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dmi_din : in std_ulogic_vector(63 downto 0);
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dmi_dout : out std_ulogic_vector(63 downto 0);
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dmi_req : in std_ulogic;
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dmi_wr : in std_ulogic;
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dmi_ack : out std_ulogic;
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-- Debug actions
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core_stop : out std_ulogic;
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core_rst : out std_ulogic;
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icache_rst : out std_ulogic;
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-- Core status inputs
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terminate : in std_ulogic;
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core_stopped : in std_ulogic;
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nia : in std_ulogic_vector(63 downto 0);
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clk : in std_logic;
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rst : in std_logic;
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dmi_addr : in std_ulogic_vector(3 downto 0);
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dmi_din : in std_ulogic_vector(63 downto 0);
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dmi_dout : out std_ulogic_vector(63 downto 0);
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dmi_req : in std_ulogic;
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dmi_wr : in std_ulogic;
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dmi_ack : out std_ulogic;
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-- Debug actions
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core_stop : out std_ulogic;
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core_rst : out std_ulogic;
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icache_rst : out std_ulogic;
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-- Core status inputs
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terminate : in std_ulogic;
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core_stopped : in std_ulogic;
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nia : in std_ulogic_vector(63 downto 0);
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msr : in std_ulogic_vector(63 downto 0);
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-- GSPR register read port
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@ -45,8 +45,8 @@ entity core_debug is
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log_read_data : out std_ulogic_vector(63 downto 0);
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log_write_addr : out std_ulogic_vector(31 downto 0);
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-- Misc
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terminated_out : out std_ulogic
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-- Misc
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terminated_out : out std_ulogic
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);
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end core_debug;
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@ -60,7 +60,7 @@ architecture behave of core_debug is
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-- bit 2 : Icache reset
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-- bit 3 : Single step
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-- bit 4 : Core start
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constant DBG_CORE_CTRL : std_ulogic_vector(3 downto 0) := "0000";
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constant DBG_CORE_CTRL : std_ulogic_vector(3 downto 0) := "0000";
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constant DBG_CORE_CTRL_STOP : integer := 0;
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constant DBG_CORE_CTRL_RESET : integer := 1;
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constant DBG_CORE_CTRL_ICRESET : integer := 2;
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@ -71,13 +71,13 @@ architecture behave of core_debug is
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-- bit 0 : Core stopping (wait til bit 1 set)
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-- bit 1 : Core stopped
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-- bit 2 : Core terminated (clears with start or reset)
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constant DBG_CORE_STAT : std_ulogic_vector(3 downto 0) := "0001";
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constant DBG_CORE_STAT : std_ulogic_vector(3 downto 0) := "0001";
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constant DBG_CORE_STAT_STOPPING : integer := 0;
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constant DBG_CORE_STAT_STOPPED : integer := 1;
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constant DBG_CORE_STAT_TERM : integer := 2;
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-- NIA register (read only for now)
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constant DBG_CORE_NIA : std_ulogic_vector(3 downto 0) := "0010";
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constant DBG_CORE_NIA : std_ulogic_vector(3 downto 0) := "0010";
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-- MSR (read only)
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constant DBG_CORE_MSR : std_ulogic_vector(3 downto 0) := "0011";
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@ -107,14 +107,14 @@ architecture behave of core_debug is
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signal do_gspr_rd : std_ulogic;
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signal gspr_index : gspr_index_t;
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signal log_dmi_addr : std_ulogic_vector(31 downto 0) := (others => '0');
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signal log_dmi_data : std_ulogic_vector(63 downto 0) := (others => '0');
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signal log_dmi_trigger : std_ulogic_vector(63 downto 0) := (others => '0');
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signal do_log_trigger : std_ulogic := '0';
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signal do_dmi_log_rd : std_ulogic;
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signal dmi_read_log_data : std_ulogic;
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signal log_dmi_addr : std_ulogic_vector(31 downto 0) := (others => '0');
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signal log_dmi_data : std_ulogic_vector(63 downto 0) := (others => '0');
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signal log_dmi_trigger : std_ulogic_vector(63 downto 0) := (others => '0');
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signal do_log_trigger : std_ulogic := '0';
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signal do_dmi_log_rd : std_ulogic;
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signal dmi_read_log_data : std_ulogic;
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signal dmi_read_log_data_1 : std_ulogic;
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signal log_trigger_delay : integer range 0 to 255 := 0;
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signal log_trigger_delay : integer range 0 to 255 := 0;
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begin
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-- Single cycle register accesses on DMI except for GSPR data
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@ -125,36 +125,36 @@ begin
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-- Status register read composition
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stat_reg <= (2 => terminated,
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1 => core_stopped,
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0 => stopping,
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others => '0');
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1 => core_stopped,
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0 => stopping,
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others => '0');
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-- DMI read data mux
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with dmi_addr select dmi_dout <=
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stat_reg when DBG_CORE_STAT,
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nia when DBG_CORE_NIA,
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stat_reg when DBG_CORE_STAT,
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nia when DBG_CORE_NIA,
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msr when DBG_CORE_MSR,
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dbg_gpr_data when DBG_CORE_GSPR_DATA,
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log_write_addr & log_dmi_addr when DBG_CORE_LOG_ADDR,
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log_dmi_data when DBG_CORE_LOG_DATA,
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log_dmi_trigger when DBG_CORE_LOG_TRIGGER,
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(others => '0') when others;
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(others => '0') when others;
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-- DMI writes
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reg_write: process(clk)
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begin
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if rising_edge(clk) then
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-- Reset the 1-cycle "do" signals
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do_step <= '0';
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do_reset <= '0';
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do_icreset <= '0';
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if rising_edge(clk) then
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-- Reset the 1-cycle "do" signals
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do_step <= '0';
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do_reset <= '0';
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do_icreset <= '0';
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do_dmi_log_rd <= '0';
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if (rst) then
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stopping <= '0';
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terminated <= '0';
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if (rst) then
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stopping <= '0';
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terminated <= '0';
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log_trigger_delay <= 0;
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else
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else
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if do_log_trigger = '1' or log_trigger_delay /= 0 then
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if log_trigger_delay = 255 then
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log_dmi_trigger(1) <= '1';
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@ -163,32 +163,32 @@ begin
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log_trigger_delay <= log_trigger_delay + 1;
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end if;
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end if;
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-- Edge detect on dmi_req for 1-shot pulses
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dmi_req_1 <= dmi_req;
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if dmi_req = '1' and dmi_req_1 = '0' then
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if dmi_wr = '1' then
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report("DMI write to " & to_hstring(dmi_addr));
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-- Control register actions
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if dmi_addr = DBG_CORE_CTRL then
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if dmi_din(DBG_CORE_CTRL_RESET) = '1' then
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do_reset <= '1';
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terminated <= '0';
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end if;
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if dmi_din(DBG_CORE_CTRL_STOP) = '1' then
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stopping <= '1';
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end if;
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if dmi_din(DBG_CORE_CTRL_STEP) = '1' then
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do_step <= '1';
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terminated <= '0';
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end if;
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if dmi_din(DBG_CORE_CTRL_ICRESET) = '1' then
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do_icreset <= '1';
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end if;
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if dmi_din(DBG_CORE_CTRL_START) = '1' then
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stopping <= '0';
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terminated <= '0';
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end if;
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-- Edge detect on dmi_req for 1-shot pulses
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dmi_req_1 <= dmi_req;
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if dmi_req = '1' and dmi_req_1 = '0' then
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if dmi_wr = '1' then
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report("DMI write to " & to_hstring(dmi_addr));
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-- Control register actions
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if dmi_addr = DBG_CORE_CTRL then
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if dmi_din(DBG_CORE_CTRL_RESET) = '1' then
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do_reset <= '1';
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terminated <= '0';
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end if;
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if dmi_din(DBG_CORE_CTRL_STOP) = '1' then
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stopping <= '1';
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end if;
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if dmi_din(DBG_CORE_CTRL_STEP) = '1' then
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do_step <= '1';
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terminated <= '0';
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end if;
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if dmi_din(DBG_CORE_CTRL_ICRESET) = '1' then
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do_icreset <= '1';
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end if;
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if dmi_din(DBG_CORE_CTRL_START) = '1' then
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stopping <= '0';
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terminated <= '0';
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end if;
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elsif dmi_addr = DBG_CORE_GSPR_INDEX then
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gspr_index <= dmi_din(gspr_index_t'left downto 0);
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elsif dmi_addr = DBG_CORE_LOG_ADDR then
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@ -196,17 +196,17 @@ begin
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do_dmi_log_rd <= '1';
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elsif dmi_addr = DBG_CORE_LOG_TRIGGER then
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log_dmi_trigger <= dmi_din;
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end if;
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else
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report("DMI read from " & to_string(dmi_addr));
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end if;
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end if;
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else
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report("DMI read from " & to_string(dmi_addr));
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end if;
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elsif dmi_read_log_data = '0' and dmi_read_log_data_1 = '1' then
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-- Increment log_dmi_addr after the end of a read from DBG_CORE_LOG_DATA
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log_dmi_addr(LOG_INDEX_BITS + 1 downto 0) <=
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std_ulogic_vector(unsigned(log_dmi_addr(LOG_INDEX_BITS+1 downto 0)) + 1);
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do_dmi_log_rd <= '1';
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end if;
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end if;
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dmi_read_log_data_1 <= dmi_read_log_data;
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if dmi_req = '1' and dmi_addr = DBG_CORE_LOG_DATA then
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dmi_read_log_data <= '1';
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@ -214,15 +214,15 @@ begin
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dmi_read_log_data <= '0';
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end if;
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-- Set core stop on terminate. We'll be stopping some time *after*
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-- the offending instruction, at least until we can do back flushes
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-- that preserve NIA which we can't just yet.
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if terminate = '1' then
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stopping <= '1';
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terminated <= '1';
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end if;
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end if;
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end if;
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-- Set core stop on terminate. We'll be stopping some time *after*
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-- the offending instruction, at least until we can do back flushes
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-- that preserve NIA which we can't just yet.
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if terminate = '1' then
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stopping <= '1';
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terminated <= '1';
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end if;
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end if;
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end if;
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end process;
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dbg_gpr_addr <= gspr_index;
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@ -237,15 +237,15 @@ begin
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maybe_log: if LOG_LENGTH > 0 generate
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subtype log_ptr_t is unsigned(LOG_INDEX_BITS - 1 downto 0);
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type log_array_t is array(0 to LOG_LENGTH - 1) of std_ulogic_vector(255 downto 0);
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signal log_array : log_array_t;
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signal log_rd_ptr : log_ptr_t;
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signal log_wr_ptr : log_ptr_t;
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signal log_toggle : std_ulogic;
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signal log_wr_enable : std_ulogic;
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signal log_array : log_array_t;
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signal log_rd_ptr : log_ptr_t;
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signal log_wr_ptr : log_ptr_t;
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signal log_toggle : std_ulogic;
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signal log_wr_enable : std_ulogic;
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signal log_rd_ptr_latched : log_ptr_t;
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signal log_rd : std_ulogic_vector(255 downto 0);
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signal log_dmi_reading : std_ulogic;
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signal log_dmi_read_done : std_ulogic;
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signal log_rd : std_ulogic_vector(255 downto 0);
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signal log_dmi_reading : std_ulogic;
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signal log_dmi_read_done : std_ulogic;
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function select_dword(data : std_ulogic_vector(255 downto 0);
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addr : std_ulogic_vector(31 downto 0)) return std_ulogic_vector is
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