Merge pull request #365 from antonblanchard/less-fpga-init

Remove some FPGA style signal inits

control.vhdl

@@ -64,8 +64,8 @@ architecture rtl of control is
 
     signal r_int, rin_int : reg_internal_type := reg_internal_init;
 
-    signal gpr_write_valid : std_ulogic := '0';
-    signal cr_write_valid  : std_ulogic := '0';
+    signal gpr_write_valid : std_ulogic;
+    signal cr_write_valid  : std_ulogic;
 
     type tag_register is record
         wr_gpr : std_ulogic;
@@ -245,6 +245,8 @@ begin
         end if;
 
         if rst = '1' then
+            gpr_write_valid <= '0';
+            cr_write_valid <= '0';
             v_int := reg_internal_init;
             valid_tmp := '0';
         end if;

core.vhdl

@@ -121,17 +121,17 @@ architecture behave of core is
     signal do_interrupt: std_ulogic;
 
     -- Delayed/Latched resets and alt_reset
-    signal rst_fetch1  : std_ulogic := '1';
-    signal rst_fetch2  : std_ulogic := '1';
-    signal rst_icache  : std_ulogic := '1';
-    signal rst_dcache  : std_ulogic := '1';
-    signal rst_dec1    : std_ulogic := '1';
-    signal rst_dec2    : std_ulogic := '1';
-    signal rst_ex1     : std_ulogic := '1';
-    signal rst_fpu     : std_ulogic := '1';
-    signal rst_ls1     : std_ulogic := '1';
-    signal rst_wback   : std_ulogic := '1';
-    signal rst_dbg     : std_ulogic := '1';
+    signal rst_fetch1  : std_ulogic;
+    signal rst_fetch2  : std_ulogic;
+    signal rst_icache  : std_ulogic;
+    signal rst_dcache  : std_ulogic;
+    signal rst_dec1    : std_ulogic;
+    signal rst_dec2    : std_ulogic;
+    signal rst_ex1     : std_ulogic;
+    signal rst_fpu     : std_ulogic;
+    signal rst_ls1     : std_ulogic;
+    signal rst_wback   : std_ulogic;
+    signal rst_dbg     : std_ulogic;
     signal alt_reset_d : std_ulogic;
 
     signal sim_cr_dump: std_ulogic;

execute1.vhdl

@@ -99,8 +99,8 @@ architecture behaviour of execute1 is
     signal mshort_p : std_ulogic_vector(31 downto 0) := (others => '0');
 
     signal valid_in : std_ulogic;
-    signal ctrl: ctrl_t := (others => (others => '0'));
-    signal ctrl_tmp: ctrl_t := (others => (others => '0'));
+    signal ctrl: ctrl_t;
+    signal ctrl_tmp: ctrl_t;
     signal right_shift, rot_clear_left, rot_clear_right: std_ulogic;
     signal rot_sign_ext: std_ulogic;
     signal rotator_result: std_ulogic_vector(63 downto 0);
@@ -406,6 +406,7 @@ begin
                 r <= reg_type_init;
                 ctrl.tb <= (others => '0');
                 ctrl.dec <= (others => '0');
+                ctrl.cfar <= (others => '0');
                 ctrl.msr <= (MSR_SF => '1', MSR_LE => '1', others => '0');
             else
                 r <= rin;

gpio.vhdl

@@ -40,8 +40,8 @@ architecture behaviour of gpio is
     constant GPIO_REG_DATA_CLR : std_ulogic_vector(GPIO_REG_BITS-1 downto 0) := "00101";
 
     -- Current output value and direction
-    signal reg_data : std_ulogic_vector(NGPIO - 1 downto 0) := (others => '0');
-    signal reg_dirn : std_ulogic_vector(NGPIO - 1 downto 0) := (others => '0');
+    signal reg_data : std_ulogic_vector(NGPIO - 1 downto 0);
+    signal reg_dirn : std_ulogic_vector(NGPIO - 1 downto 0);
     signal reg_in1  : std_ulogic_vector(NGPIO - 1 downto 0);
     signal reg_in2  : std_ulogic_vector(NGPIO - 1 downto 0);
 

soc.vhdl

@@ -223,15 +223,15 @@ architecture behaviour of soc is
     signal dmi_core_ack   : std_ulogic;
 
     -- Delayed/latched resets and alt_reset
-    signal rst_core    : std_ulogic := '1';
-    signal rst_uart    : std_ulogic := '1';
-    signal rst_xics    : std_ulogic := '1';
-    signal rst_spi     : std_ulogic := '1';
-    signal rst_gpio    : std_ulogic := '1';
-    signal rst_bram    : std_ulogic := '1';
-    signal rst_dtm     : std_ulogic := '1';
-    signal rst_wbar    : std_ulogic := '1';
-    signal rst_wbdb    : std_ulogic := '1';
+    signal rst_core    : std_ulogic;
+    signal rst_uart    : std_ulogic;
+    signal rst_xics    : std_ulogic;
+    signal rst_spi     : std_ulogic;
+    signal rst_gpio    : std_ulogic;
+    signal rst_bram    : std_ulogic;
+    signal rst_dtm     : std_ulogic;
+    signal rst_wbar    : std_ulogic;
+    signal rst_wbdb    : std_ulogic;
     signal alt_reset_d : std_ulogic;
 
     -- IO branch split:

spi_flash_ctrl.vhdl

@@ -50,7 +50,7 @@ architecture rtl of spi_flash_ctrl is
     constant SPI_REG_INVALID      : std_ulogic_vector(SPI_REG_BITS-1 downto 0) := "111";
 
     -- Control register
-    signal ctrl_reg    : std_ulogic_vector(15 downto 0) := (others => '0');
+    signal ctrl_reg    : std_ulogic_vector(15 downto 0);
     alias  ctrl_reset  : std_ulogic is ctrl_reg(0);
     alias  ctrl_cs     : std_ulogic is ctrl_reg(1);
     alias  ctrl_rsrv1  : std_ulogic is ctrl_reg(2);
@@ -58,7 +58,7 @@ architecture rtl of spi_flash_ctrl is
     alias  ctrl_div    : std_ulogic_vector(7 downto 0) is ctrl_reg(15 downto 8);
 
     -- Auto mode config register
-    signal auto_cfg_reg     : std_ulogic_vector(29 downto 0) := (others => '0');
+    signal auto_cfg_reg     : std_ulogic_vector(29 downto 0);
     alias  auto_cfg_cmd     : std_ulogic_vector(7 downto 0) is auto_cfg_reg(7 downto 0);
     alias  auto_cfg_dummies : std_ulogic_vector(2 downto 0) is auto_cfg_reg(10 downto 8);
     alias  auto_cfg_mode    : std_ulogic_vector(1 downto 0) is auto_cfg_reg(12 downto 11);
@@ -126,9 +126,9 @@ architecture rtl of spi_flash_ctrl is
     signal auto_latch_adr : std_ulogic;
 
     -- Automatic mode latches
-    signal auto_data      : std_ulogic_vector(wb_out.dat'left downto 0) := (others => '0');
-    signal auto_cnt       : integer range 0 to 63 := 0;
-    signal auto_state     : auto_state_t := AUTO_BOOT;
+    signal auto_data      : std_ulogic_vector(wb_out.dat'left downto 0);
+    signal auto_cnt       : integer range 0 to 63;
+    signal auto_state     : auto_state_t;
     signal auto_last_addr : std_ulogic_vector(31 downto 0);
 
 begin
@@ -351,6 +351,8 @@ begin
             if rst = '1' then
                 auto_last_addr <= (others => '0');
                 auto_state <= AUTO_BOOT;
+                auto_cnt <= 0;
+                auto_data  <= (others => '0');
             else
                 auto_state <= auto_next;
                 auto_cnt   <= auto_cnt_next;

spi_rxtx.vhdl

@@ -126,10 +126,10 @@ architecture rtl of spi_rxtx is
     signal dat_ack_l : std_ulogic;
 
     -- Delayed recv signal for the read machine
-    signal sck_recv_d : std_ulogic := '0';
+    signal sck_recv_d : std_ulogic;
 
     -- Input shift register (use fifo ?)
-    signal ireg       : std_ulogic_vector(7 downto 0) := (others => '0');
+    signal ireg       : std_ulogic_vector(7 downto 0);
 
     -- Bit counter
     signal bit_count  : std_ulogic_vector(2 downto 0);
@@ -157,7 +157,7 @@ architecture rtl of spi_rxtx is
     end;
 
     type state_t is (STANDBY, DATA);
-    signal state : state_t := STANDBY;
+    signal state : state_t;
 begin
 
     -- We don't support multiple data lines at this point
@@ -349,6 +349,9 @@ begin
     shift_in: process(clk)
     begin
         if rising_edge(clk) then
+            if rst = '1' then
+                ireg <= (others => '0');
+            end if;
 
             -- Delay the receive signal to match the input latch
             if state = DATA then