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@ -17,7 +17,8 @@ entity toplevel is
@@ -17,7 +17,8 @@ entity toplevel is
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ICACHE_NUM_LINES : natural := 64; |
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LOG_LENGTH : natural := 512; |
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DISABLE_FLATTEN_CORE : boolean := false; |
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UART_IS_16550 : boolean := true |
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UART_IS_16550 : boolean := true; |
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HAS_LPC : boolean := true |
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); |
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port( |
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ext_clk : in std_ulogic; |
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@ -25,7 +26,19 @@ entity toplevel is
@@ -25,7 +26,19 @@ entity toplevel is
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-- UART0 signals: |
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uart0_txd : out std_ulogic; |
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uart0_rxd : in std_ulogic |
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uart0_rxd : in std_ulogic; |
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-- LPC |
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lpc_clock : in std_ulogic; |
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lpc_frame_n : in std_ulogic; |
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lpc_reset_n : in std_ulogic; |
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lpc_data_i : in std_ulogic_vector(3 downto 0); |
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lpc_irq_i : in std_ulogic; |
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lpc_data_oe : out std_ulogic; |
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lpc_data_o_reg : out std_ulogic_vector(3 downto 0); |
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lpc_irq_o2 : out std_ulogic |
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); |
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end entity toplevel; |
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@ -39,6 +52,11 @@ architecture behaviour of toplevel is
@@ -39,6 +52,11 @@ architecture behaviour of toplevel is
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signal system_clk : std_ulogic; |
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signal system_clk_locked : std_ulogic; |
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-- LPC |
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signal lpc_data_i_reg : std_ulogic_vector(3 downto 0); |
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signal lpc_data_o : std_ulogic_vector(3 downto 0); |
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signal lpc_irq_o : std_ulogic; |
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signal lpc_irq_oe : std_ulogic; |
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begin |
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reset_controller: entity work.soc_reset |
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@ -79,13 +97,35 @@ begin
@@ -79,13 +97,35 @@ begin
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ICACHE_NUM_LINES => ICACHE_NUM_LINES, |
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LOG_LENGTH => LOG_LENGTH, |
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DISABLE_FLATTEN_CORE => DISABLE_FLATTEN_CORE, |
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UART0_IS_16550 => UART_IS_16550 |
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UART0_IS_16550 => UART_IS_16550, |
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HAS_LPC => HAS_LPC |
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) |
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port map ( |
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system_clk => system_clk, |
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rst => soc_rst, |
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uart0_txd => uart0_txd, |
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uart0_rxd => uart0_rxd |
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uart0_rxd => uart0_rxd, |
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-- LPC |
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lpc_data_o => lpc_data_o, |
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lpc_data_oe => lpc_data_oe, |
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lpc_data_i => lpc_data_i, |
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lpc_frame_n => lpc_frame_n, |
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lpc_reset_n => lpc_reset_n, |
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lpc_clock => lpc_clock, |
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lpc_irq_o => lpc_irq_o, |
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lpc_irq_oe => lpc_irq_oe, |
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lpc_irq_i => lpc_irq_i |
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); |
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process(lpc_clock) |
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begin |
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if rising_edge(lpc_clock) then |
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lpc_data_i_reg <= lpc_data_i; |
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lpc_data_o_reg <= lpc_data_o when lpc_data_oe = '1' and ext_rst = '1' else "ZZZZ"; |
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end if; |
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end process; |
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lpc_irq_o2 <= lpc_irq_o when lpc_irq_oe = '1' and ext_rst = '1' else 'Z'; |
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end architecture behaviour; |
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