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@ -63,7 +63,6 @@ architecture behave of loadstore1 is
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load : std_ulogic;
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tlbie : std_ulogic;
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dcbz : std_ulogic;
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mfspr : std_ulogic;
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addr : std_ulogic_vector(63 downto 0);
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store_data : std_ulogic_vector(63 downto 0);
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load_data : std_ulogic_vector(63 downto 0);
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@ -105,6 +104,7 @@ architecture behave of loadstore1 is
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ld_sp_nz : std_ulogic;
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ld_sp_lz : std_ulogic_vector(5 downto 0);
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st_sp_data : std_ulogic_vector(31 downto 0);
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wr_sel : std_ulogic_vector(1 downto 0);
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end record;
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signal r, rin : reg_stage_t;
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@ -312,20 +312,18 @@ begin
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variable itlb_fault : std_ulogic;
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variable misaligned : std_ulogic;
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variable fp_reg_conv : std_ulogic;
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variable lfs_done : std_ulogic;
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begin
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v := r;
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req := '0';
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v.mfspr := '0';
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mmu_mtspr := '0';
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itlb_fault := '0';
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sprn := std_ulogic_vector(to_unsigned(decode_spr_num(l_in.insn), 10));
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dsisr := (others => '0');
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mmureq := '0';
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fp_reg_conv := '0';
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v.wr_sel := "11";
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write_enable := '0';
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lfs_done := '0';
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do_update := r.do_update;
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v.do_update := '0';
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@ -447,6 +445,11 @@ begin
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v.last_dword := '0';
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when ACK_WAIT =>
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-- r.wr_sel gets set one cycle after we come into ACK_WAIT state,
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-- which is OK because the dcache always takes at least two cycles.
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if r.update = '1' and (r.load = '0' or (HAS_FPU and r.load_sp = '1')) then
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v.wr_sel := "01";
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end if;
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if d_in.error = '1' then
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-- dcache will discard the second request if it
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-- gets an error on the 1st of two requests
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@ -477,9 +480,11 @@ begin
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-- SP to DP conversion takes a cycle
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-- Write back rA update in this cycle if needed
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do_update := r.update;
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v.wr_sel := "10";
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v.state := FINISH_LFS;
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elsif r.extra_cycle = '1' then
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-- loads with rA update need an extra cycle
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v.wr_sel := "01";
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v.state := COMPLETE;
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v.do_update := r.update;
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else
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@ -517,7 +522,6 @@ begin
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when TLBIE_WAIT =>
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when FINISH_LFS =>
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lfs_done := '1';
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when COMPLETE =>
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exception := r.align_intr;
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@ -631,7 +635,7 @@ begin
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v.state := TLBIE_WAIT;
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v.wait_mmu := '1';
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when OP_MFSPR =>
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v.mfspr := '1';
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v.wr_sel := "00";
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-- partial decode on SPR number should be adequate given
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-- the restricted set that get sent down this path
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if sprn(9) = '0' and sprn(5) = '0' then
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@ -738,23 +742,24 @@ begin
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-- Multiplex either cache data to the destination GPR or
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-- the address for the rA update.
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l_out.valid <= done;
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if r.mfspr = '1' then
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case r.wr_sel is
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when "00" =>
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l_out.write_enable <= '1';
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l_out.write_reg <= r.write_reg;
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l_out.write_data <= r.sprval;
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elsif do_update = '1' then
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l_out.write_enable <= '1';
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when "01" =>
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l_out.write_enable <= do_update;
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l_out.write_reg <= gpr_to_gspr(r.update_reg);
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l_out.write_data <= r.addr;
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elsif lfs_done = '1' then
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when "10" =>
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l_out.write_enable <= '1';
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l_out.write_reg <= r.write_reg;
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l_out.write_data <= load_dp_data;
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else
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when others =>
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l_out.write_enable <= write_enable;
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l_out.write_reg <= r.write_reg;
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l_out.write_data <= data_trimmed;
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end if;
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end case;
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l_out.xerc <= r.xerc;
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l_out.rc <= r.rc and done;
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l_out.store_done <= d_in.store_done;
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