fpga/bram: Generate stall signal

This doesn't yet pipeline the block RAM, just generate a valid stall signal so it's compatible with a pipelined master Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago · e638c3e8ae
parent 37acb35773
commit e638c3e8ae
1 changed files with 2 additions and 1 deletions
--- a/fpga/mw_soc_memory.vhdl
+++ b/fpga/mw_soc_memory.vhdl
@ -65,7 +65,8 @@ begin

    wb_adr_in <= wishbone_in.adr(log2(MEMORY_SIZE) - 1 downto 0);

-    wishbone_out.ack <= read_ack and wishbone_in.stb;
+    wishbone_out.ack <= read_ack and wishbone_in.cyc and wishbone_in.stb;
+    wishbone_out.stall <= '0' when wishbone_in.cyc = '0' else not wishbone_out.ack;

    memory_0: process(clk)
    begin