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@ -205,7 +205,7 @@ architecture rtl of icache is
@@ -205,7 +205,7 @@ architecture rtl of icache is
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signal req_tag : cache_tag_t; |
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signal req_is_hit : std_ulogic; |
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signal req_is_miss : std_ulogic; |
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signal req_laddr : std_ulogic_vector(63 downto 0); |
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signal req_raddr : real_addr_t; |
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signal tlb_req_index : tlb_index_t; |
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signal real_addr : real_addr_t; |
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@ -235,7 +235,7 @@ architecture rtl of icache is
@@ -235,7 +235,7 @@ architecture rtl of icache is
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end; |
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-- Return the cache row index (data memory) for an address |
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function get_row(addr: std_ulogic_vector(63 downto 0)) return row_t is |
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function get_row(addr: std_ulogic_vector) return row_t is |
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begin |
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return to_integer(unsigned(addr(SET_SIZE_BITS - 1 downto ROW_OFF_BITS))); |
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end; |
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@ -521,8 +521,7 @@ begin
@@ -521,8 +521,7 @@ begin
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-- Calculate address of beginning of cache row, will be |
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-- used for cache miss processing if needed |
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-- |
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req_laddr <= (63 downto REAL_ADDR_BITS => '0') & |
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real_addr(REAL_ADDR_BITS - 1 downto ROW_OFF_BITS) & |
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req_raddr <= real_addr(REAL_ADDR_BITS - 1 downto ROW_OFF_BITS) & |
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(ROW_OFF_BITS-1 downto 0 => '0'); |
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-- Test if pending request is a hit on any way |
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@ -705,15 +704,15 @@ begin
@@ -705,15 +704,15 @@ begin
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-- Keep track of our index and way for subsequent stores |
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r.store_index <= req_index; |
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r.store_row <= get_row(req_laddr); |
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r.store_row <= get_row(req_raddr); |
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r.store_tag <= req_tag; |
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r.store_valid <= '1'; |
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r.end_row_ix <= get_row_of_line(get_row(req_laddr)) - 1; |
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r.end_row_ix <= get_row_of_line(get_row(req_raddr)) - 1; |
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-- Prep for first wishbone read. We calculate the address of |
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-- the start of the cache line and start the WB cycle. |
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-- |
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r.wb.adr <= addr_to_wb(req_laddr); |
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r.wb.adr <= addr_to_wb(req_raddr); |
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r.wb.cyc <= '1'; |
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r.wb.stb <= '1'; |
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