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@ -6,106 +6,106 @@ library work;
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use work.common.all;
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entity writeback is
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port (
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clk : in std_ulogic;
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port (
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clk : in std_ulogic;
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e_in : in Execute2ToWritebackType;
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l_in : in Loadstore2ToWritebackType;
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m_in : in MultiplyToWritebackType;
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e_in : in Execute2ToWritebackType;
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l_in : in Loadstore2ToWritebackType;
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m_in : in MultiplyToWritebackType;
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w_out : out WritebackToRegisterFileType;
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c_out : out WritebackToCrFileType;
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w_out : out WritebackToRegisterFileType;
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c_out : out WritebackToCrFileType;
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complete_out : out std_ulogic
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);
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complete_out : out std_ulogic
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);
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end entity writeback;
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architecture behaviour of writeback is
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type reg_internal_type is record
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complete : std_ulogic;
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end record;
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type reg_type is record
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w : WritebackToRegisterFileType;
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c : WritebackToCrFileType;
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end record;
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signal r, rin : reg_type;
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signal r_int, rin_int : reg_internal_type;
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type reg_internal_type is record
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complete : std_ulogic;
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end record;
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type reg_type is record
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w : WritebackToRegisterFileType;
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c : WritebackToCrFileType;
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end record;
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signal r, rin : reg_type;
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signal r_int, rin_int : reg_internal_type;
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begin
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writeback_0: process(clk)
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begin
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if rising_edge(clk) then
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r <= rin;
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r_int <= rin_int;
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end if;
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end process;
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writeback_1: process(all)
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variable x: std_ulogic_vector(0 downto 0);
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variable y: std_ulogic_vector(0 downto 0);
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variable z: std_ulogic_vector(0 downto 0);
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variable v : reg_type;
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variable v_int : reg_internal_type;
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begin
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v := r;
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v_int := r_int;
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x := "" & e_in.valid;
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y := "" & l_in.valid;
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z := "" & m_in.valid;
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assert (to_integer(unsigned(x)) + to_integer(unsigned(y)) + to_integer(unsigned(z))) <= 1 severity failure;
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x := "" & e_in.write_enable;
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y := "" & l_in.write_enable;
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z := "" & m_in.write_reg_enable;
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assert (to_integer(unsigned(x)) + to_integer(unsigned(y)) + to_integer(unsigned(z))) <= 1 severity failure;
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assert not(e_in.write_cr_enable = '1' and m_in.write_cr_enable = '1');
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v.w := WritebackToRegisterFileInit;
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v.c := WritebackToCrFileInit;
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v_int.complete := '0';
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if e_in.valid = '1' or l_in.valid = '1' or m_in.valid = '1' then
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v_int.complete := '1';
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end if;
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if e_in.write_enable = '1' then
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v.w.write_reg := e_in.write_reg;
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v.w.write_data := e_in.write_data;
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v.w.write_enable := '1';
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end if;
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if e_in.write_cr_enable = '1' then
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v.c.write_cr_enable := '1';
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v.c.write_cr_mask := e_in.write_cr_mask;
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v.c.write_cr_data := e_in.write_cr_data;
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end if;
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if l_in.write_enable = '1' then
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v.w.write_reg := l_in.write_reg;
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v.w.write_data := l_in.write_data;
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v.w.write_enable := '1';
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end if;
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if m_in.write_reg_enable = '1' then
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v.w.write_enable := '1';
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v.w.write_reg := m_in.write_reg_nr;
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v.w.write_data := m_in.write_reg_data;
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end if;
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if m_in.write_cr_enable = '1' then
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v.c.write_cr_enable := '1';
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v.c.write_cr_mask := m_in.write_cr_mask;
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v.c.write_cr_data := m_in.write_cr_data;
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end if;
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-- Update registers
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rin <= v;
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rin_int <= v_int;
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-- Update outputs
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complete_out <= r_int.complete;
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w_out <= r.w;
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c_out <= r.c;
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end process;
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writeback_0: process(clk)
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begin
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if rising_edge(clk) then
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r <= rin;
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r_int <= rin_int;
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end if;
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end process;
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writeback_1: process(all)
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variable x : std_ulogic_vector(0 downto 0);
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variable y : std_ulogic_vector(0 downto 0);
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variable z : std_ulogic_vector(0 downto 0);
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variable v : reg_type;
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variable v_int : reg_internal_type;
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begin
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v := r;
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v_int := r_int;
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x := "" & e_in.valid;
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y := "" & l_in.valid;
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z := "" & m_in.valid;
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assert (to_integer(unsigned(x)) + to_integer(unsigned(y)) + to_integer(unsigned(z))) <= 1 severity failure;
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x := "" & e_in.write_enable;
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y := "" & l_in.write_enable;
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z := "" & m_in.write_reg_enable;
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assert (to_integer(unsigned(x)) + to_integer(unsigned(y)) + to_integer(unsigned(z))) <= 1 severity failure;
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assert not(e_in.write_cr_enable = '1' and m_in.write_cr_enable = '1');
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v.w := WritebackToRegisterFileInit;
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v.c := WritebackToCrFileInit;
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v_int.complete := '0';
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if e_in.valid = '1' or l_in.valid = '1' or m_in.valid = '1' then
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v_int.complete := '1';
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end if;
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if e_in.write_enable = '1' then
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v.w.write_reg := e_in.write_reg;
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v.w.write_data := e_in.write_data;
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v.w.write_enable := '1';
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end if;
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if e_in.write_cr_enable = '1' then
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v.c.write_cr_enable := '1';
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v.c.write_cr_mask := e_in.write_cr_mask;
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v.c.write_cr_data := e_in.write_cr_data;
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end if;
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if l_in.write_enable = '1' then
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v.w.write_reg := l_in.write_reg;
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v.w.write_data := l_in.write_data;
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v.w.write_enable := '1';
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end if;
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if m_in.write_reg_enable = '1' then
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v.w.write_enable := '1';
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v.w.write_reg := m_in.write_reg_nr;
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v.w.write_data := m_in.write_reg_data;
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end if;
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if m_in.write_cr_enable = '1' then
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v.c.write_cr_enable := '1';
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v.c.write_cr_mask := m_in.write_cr_mask;
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v.c.write_cr_data := m_in.write_cr_data;
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end if;
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-- Update registers
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rin <= v;
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rin_int <= v_int;
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-- Update outputs
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complete_out <= r_int.complete;
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w_out <= r.w;
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c_out <= r.c;
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end process;
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end;
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Anton Blanchard
