Remove execute2 stage

Since the condition setting got moved to writeback, execute2 does
nothing aside from wasting a cycle.  This removes it.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
jtag-port
Paul Mackerras 5 years ago
parent 9646fe28b0
commit f49a5a99a5

@ -17,7 +17,7 @@ common.o: decode_types.o
control.o: gpr_hazard.o cr_hazard.o
sim_jtag.o: sim_jtag_socket.o
core_tb.o: common.o wishbone_types.o core.o soc.o sim_jtag.o
core.o: common.o wishbone_types.o fetch1.o fetch2.o icache.o decode1.o decode2.o register_file.o cr_file.o execute1.o execute2.o loadstore1.o loadstore2.o multiply.o writeback.o core_debug.o divider.o
core.o: common.o wishbone_types.o fetch1.o fetch2.o icache.o decode1.o decode2.o register_file.o cr_file.o execute1.o loadstore1.o loadstore2.o multiply.o writeback.o core_debug.o divider.o
core_debug.o: common.o
countzero.o:
countzero_tb.o: common.o glibc_random.o countzero.o
@ -27,7 +27,6 @@ decode1.o: common.o decode_types.o
decode2.o: decode_types.o common.o helpers.o insn_helpers.o control.o
decode_types.o:
execute1.o: decode_types.o common.o helpers.o crhelpers.o insn_helpers.o ppc_fx_insns.o rotator.o logical.o countzero.o
execute2.o: common.o
fetch1.o: common.o
fetch2.o: common.o wishbone_types.o
glibc_random_helpers.o:

@ -164,21 +164,7 @@ package common is
end record;
constant Loadstore2ToWritebackInit : Loadstore2ToWritebackType := (valid => '0', write_enable => '0', sign_extend => '0', byte_reverse => '0', second_word => '0', others => (others => '0'));

type Execute1ToExecute2Type is record
valid: std_ulogic;
write_enable : std_ulogic;
write_reg: std_ulogic_vector(4 downto 0);
write_data: std_ulogic_vector(63 downto 0);
write_len : std_ulogic_vector(3 downto 0);
write_cr_enable : std_ulogic;
write_cr_mask : std_ulogic_vector(7 downto 0);
write_cr_data : std_ulogic_vector(31 downto 0);
rc : std_ulogic;
sign_extend: std_ulogic;
end record;
constant Execute1ToExecute2Init : Execute1ToExecute2Type := (valid => '0', write_enable => '0', write_cr_enable => '0', rc => '0', sign_extend => '0', others => (others => '0'));

type Execute2ToWritebackType is record
type Execute1ToWritebackType is record
valid: std_ulogic;
rc : std_ulogic;
write_enable : std_ulogic;
@ -190,7 +176,7 @@ package common is
write_cr_data : std_ulogic_vector(31 downto 0);
sign_extend: std_ulogic;
end record;
constant Execute2ToWritebackInit : Execute2ToWritebackType := (valid => '0', rc => '0', write_enable => '0', write_cr_enable => '0', sign_extend => '0', others => (others => '0'));
constant Execute1ToWritebackInit : Execute1ToWritebackType := (valid => '0', rc => '0', write_enable => '0', write_cr_enable => '0', sign_extend => '0', others => (others => '0'));

type MultiplyToWritebackType is record
valid: std_ulogic;

@ -54,8 +54,7 @@ architecture behave of core is
signal writeback_to_cr_file: WritebackToCrFileType;

-- execute signals
signal execute1_to_execute2: Execute1ToExecute2Type;
signal execute2_to_writeback: Execute2ToWritebackType;
signal execute1_to_writeback: Execute1ToWritebackType;
signal execute1_to_fetch1: Execute1ToFetch1Type;

-- load store signals
@ -204,17 +203,10 @@ begin
flush_out => flush,
e_in => decode2_to_execute1,
f_out => execute1_to_fetch1,
e_out => execute1_to_execute2,
e_out => execute1_to_writeback,
terminate_out => terminate
);

execute2_0: entity work.execute2
port map (
clk => clk,
e_in => execute1_to_execute2,
e_out => execute2_to_writeback
);

loadstore1_0: entity work.loadstore1
port map (
clk => clk,
@ -249,7 +241,7 @@ begin
writeback_0: entity work.writeback
port map (
clk => clk,
e_in => execute2_to_writeback,
e_in => execute1_to_writeback,
l_in => loadstore2_to_writeback,
m_in => multiply_to_writeback,
d_in => divider_to_writeback,

@ -25,7 +25,7 @@ entity execute1 is
-- asynchronous
f_out : out Execute1ToFetch1Type;

e_out : out Execute1ToExecute2Type;
e_out : out Execute1ToWritebackType;

terminate_out : out std_ulogic
);
@ -34,7 +34,7 @@ end entity execute1;
architecture behaviour of execute1 is
type reg_type is record
--f : Execute1ToFetch1Type;
e : Execute1ToExecute2Type;
e : Execute1ToWritebackType;
end record;

signal r, rin : reg_type;
@ -124,7 +124,7 @@ begin
newcrf := (others => '0');

v := r;
v.e := Execute1ToExecute2Init;
v.e := Execute1ToWritebackInit;
--v.f := Execute1ToFetch1TypeInit;

ctrl_tmp <= ctrl;

@ -1,52 +0,0 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library work;
use work.common.all;

-- 2 cycle ALU
-- We handle rc form instructions here

entity execute2 is
port (
clk : in std_ulogic;

e_in : in Execute1ToExecute2Type;
e_out : out Execute2ToWritebackType
);
end execute2;

architecture behave of execute2 is
signal r, rin : Execute2ToWritebackType;
begin
execute2_0: process(clk)
begin
if rising_edge(clk) then
r <= rin;
end if;
end process;

execute2_1: process(all)
variable v : Execute2ToWritebackType;
begin
v := rin;

v.valid := e_in.valid;
v.write_enable := e_in.write_enable;
v.write_reg := e_in.write_reg;
v.write_data := e_in.write_data;
v.write_cr_enable := e_in.write_cr_enable;
v.write_cr_mask := e_in.write_cr_mask;
v.write_cr_data := e_in.write_cr_data;
v.rc := e_in.rc;
v.write_len := e_in.write_len;
v.sign_extend := e_in.sign_extend;

-- Update registers
rin <= v;

-- Update outputs
e_out <= r;
end process;
end;

@ -24,7 +24,6 @@ filesets:
- cr_hazard.vhdl
- control.vhdl
- execute1.vhdl
- execute2.vhdl
- loadstore1.vhdl
- loadstore2.vhdl
- multiply.vhdl

@ -10,7 +10,7 @@ entity writeback is
port (
clk : in std_ulogic;

e_in : in Execute2ToWritebackType;
e_in : in Execute1ToWritebackType;
l_in : in Loadstore2ToWritebackType;
m_in : in MultiplyToWritebackType;
d_in : in DividerToWritebackType;

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