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@ -23,7 +23,7 @@ architecture behave of rotator_tb is
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signal shift: std_ulogic_vector(6 downto 0) := (others => '0');
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signal insn: std_ulogic_vector(31 downto 0) := (others => '0');
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signal is_32bit, right_shift, arith, clear_left, clear_right: std_ulogic := '0';
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signal result: std_ulogic_vector(63 downto 0);
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signal res: std_ulogic_vector(63 downto 0);
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signal carry_out: std_ulogic;
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signal extsw: std_ulogic;
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@ -40,7 +40,7 @@ begin
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clear_left => clear_left,
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clear_right => clear_right,
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sign_ext_rs => extsw,
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result => result,
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result => res,
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carry_out => carry_out
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);
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@ -50,7 +50,11 @@ begin
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variable rnd : RandomPType;
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begin
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rnd.InitSeed(stim_process'path_name);
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-- TODO: Consider making debug messages visible with a command line option
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-- rather than uncommenting this line:
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-- show(display_handler, debug);
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test_runner_setup(runner, runner_cfg);
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while test_suite loop
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@ -68,8 +72,7 @@ begin
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insn <= x"00000" & '0' & rnd.RandSlv(10) & '0';
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wait for clk_period;
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behave_ra := ppc_rlwinm(rs, shift(4 downto 0), insn_mb32(insn), insn_me32(insn));
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assert behave_ra = result
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report "bad rlwnm expected " & to_hstring(behave_ra) & " got " & to_hstring(result);
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check_equal(res, behave_ra, result("for rlwnm"));
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end loop;
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elsif run("Test rlwimi") then
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@ -85,8 +88,7 @@ begin
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insn <= x"00000" & '0' & rnd.RandSlv(10) & '0';
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wait for clk_period;
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behave_ra := ppc_rlwimi(ra, rs, shift(4 downto 0), insn_mb32(insn), insn_me32(insn));
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assert behave_ra = result
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report "bad rlwimi expected " & to_hstring(behave_ra) & " got " & to_hstring(result);
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check_equal(res, behave_ra, result("for rlwnimi"));
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end loop;
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elsif run("Test rld[i]cl") then
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@ -102,8 +104,7 @@ begin
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insn <= x"00000" & '0' & rnd.RandSlv(10) & '0';
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wait for clk_period;
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behave_ra := ppc_rldicl(rs, shift(5 downto 0), insn_mb(insn));
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assert behave_ra = result
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report "bad rldicl expected " & to_hstring(behave_ra) & " got " & to_hstring(result);
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check_equal(res, behave_ra, result("for rldicl"));
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end loop;
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elsif run("Test rld[i]cr") then
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@ -119,13 +120,12 @@ begin
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insn <= x"00000" & '0' & rnd.RandSlv(10) & '0';
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wait for clk_period;
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behave_ra := ppc_rldicr(rs, shift(5 downto 0), insn_me(insn));
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--report "rs = " & to_hstring(rs);
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--report "ra = " & to_hstring(ra);
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--report "shift = " & to_hstring(shift);
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--report "insn me = " & to_hstring(insn_me(insn));
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--report "result = " & to_hstring(result);
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assert behave_ra = result
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report "bad rldicr expected " & to_hstring(behave_ra) & " got " & to_hstring(result);
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debug("rs = " & to_hstring(rs));
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debug("ra = " & to_hstring(ra));
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debug("shift = " & to_hstring(shift));
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debug("insn me = " & to_hstring(insn_me(insn)));
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debug("result = " & to_hstring(res));
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check_equal(res, behave_ra, result("for rldicr"));
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end loop;
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elsif run("Test rldic") then
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@ -141,8 +141,7 @@ begin
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insn <= x"00000" & '0' & rnd.RandSlv(10) & '0';
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wait for clk_period;
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behave_ra := ppc_rldic(rs, shift(5 downto 0), insn_mb(insn));
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assert behave_ra = result
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report "bad rldic expected " & to_hstring(behave_ra) & " got " & to_hstring(result);
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check_equal(res, behave_ra, result("for rldic"));
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end loop;
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elsif run("Test rldimi") then
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@ -158,8 +157,7 @@ begin
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insn <= x"00000" & '0' & rnd.RandSlv(10) & '0';
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wait for clk_period;
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behave_ra := ppc_rldimi(ra, rs, shift(5 downto 0), insn_mb(insn));
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assert behave_ra = result
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report "bad rldimi expected " & to_hstring(behave_ra) & " got " & to_hstring(result);
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check_equal(res, behave_ra, result("for rldimi"));
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end loop;
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elsif run("Test slw") then
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@ -174,8 +172,7 @@ begin
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shift <= rnd.RandSlv(7);
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wait for clk_period;
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behave_ra := ppc_slw(rs, std_ulogic_vector(resize(unsigned(shift), 64)));
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assert behave_ra = result
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report "bad slw expected " & to_hstring(behave_ra) & " got " & to_hstring(result);
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check_equal(res, behave_ra, result("for slv"));
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end loop;
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elsif run("Test sld") then
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@ -190,8 +187,7 @@ begin
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shift <= rnd.RandSlv(7);
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wait for clk_period;
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behave_ra := ppc_sld(rs, std_ulogic_vector(resize(unsigned(shift), 64)));
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assert behave_ra = result
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report "bad sld expected " & to_hstring(behave_ra) & " got " & to_hstring(result);
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check_equal(res, behave_ra, result("for sld"));
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end loop;
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elsif run("Test srw") then
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@ -206,8 +202,7 @@ begin
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shift <= rnd.RandSlv(7);
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wait for clk_period;
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behave_ra := ppc_srw(rs, std_ulogic_vector(resize(unsigned(shift), 64)));
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assert behave_ra = result
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report "bad srw expected " & to_hstring(behave_ra) & " got " & to_hstring(result);
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check_equal(res, behave_ra, result("for srw"));
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end loop;
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elsif run("Test srd") then
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@ -222,8 +217,7 @@ begin
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shift <= rnd.RandSlv(7);
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wait for clk_period;
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behave_ra := ppc_srd(rs, std_ulogic_vector(resize(unsigned(shift), 64)));
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assert behave_ra = result
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report "bad srd expected " & to_hstring(behave_ra) & " got " & to_hstring(result);
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check_equal(res, behave_ra, result("for srd"));
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end loop;
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elsif run("Test sraw[i]") then
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@ -238,12 +232,12 @@ begin
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shift <= '0' & rnd.RandSlv(6);
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wait for clk_period;
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behave_ca_ra := ppc_sraw(rs, std_ulogic_vector(resize(unsigned(shift), 64)));
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--report "rs = " & to_hstring(rs);
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--report "ra = " & to_hstring(ra);
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--report "shift = " & to_hstring(shift);
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--report "result = " & to_hstring(carry_out & result);
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assert behave_ca_ra(63 downto 0) = result and behave_ca_ra(64) = carry_out
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report "bad sraw expected " & to_hstring(behave_ca_ra) & " got " & to_hstring(carry_out & result);
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debug("rs = " & to_hstring(rs));
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debug("ra = " & to_hstring(ra));
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debug("shift = " & to_hstring(shift));
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debug("result = " & to_hstring(carry_out & res));
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check_equal(res, behave_ca_ra(63 downto 0), result("for sraw"));
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check_equal(carry_out, behave_ca_ra(64), result("for sraw carry_out"));
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end loop;
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elsif run("Test srad[i]") then
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@ -258,12 +252,12 @@ begin
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shift <= rnd.RandSlv(7);
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wait for clk_period;
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behave_ca_ra := ppc_srad(rs, std_ulogic_vector(resize(unsigned(shift), 64)));
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--report "rs = " & to_hstring(rs);
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--report "ra = " & to_hstring(ra);
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--report "shift = " & to_hstring(shift);
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--report "result = " & to_hstring(carry_out & result);
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assert behave_ca_ra(63 downto 0) = result and behave_ca_ra(64) = carry_out
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report "bad srad expected " & to_hstring(behave_ca_ra) & " got " & to_hstring(carry_out & result);
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debug("rs = " & to_hstring(rs));
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debug("ra = " & to_hstring(ra));
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debug("shift = " & to_hstring(shift));
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debug("result = " & to_hstring(carry_out & res));
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check_equal(res, behave_ca_ra(63 downto 0), result("for srad"));
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check_equal(carry_out, behave_ca_ra(64), result("for srad carry_out"));
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end loop;
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elsif run("Test extswsli") then
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@ -282,12 +276,11 @@ begin
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behave_ra(63 downto 32) := (others => rs(31));
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behave_ra := std_ulogic_vector(shift_left(unsigned(behave_ra),
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to_integer(unsigned(shift))));
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--report "rs = " & to_hstring(rs);
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--report "ra = " & to_hstring(ra);
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--report "shift = " & to_hstring(shift);
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--report "result = " & to_hstring(carry_out & result);
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assert behave_ra = result
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report "bad extswsli expected " & to_hstring(behave_ra) & " got " & to_hstring(result);
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debug("rs = " & to_hstring(rs));
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debug("ra = " & to_hstring(ra));
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debug("shift = " & to_hstring(shift));
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debug("result = " & to_hstring(carry_out & res));
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check_equal(res, behave_ra, result("for extswsli"));
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end loop;
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end if;
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end loop;
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