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@ -440,8 +440,12 @@ architecture rtl of dcache is
@@ -440,8 +440,12 @@ architecture rtl of dcache is
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function read_tlb_tag(way: tlb_way_t; tags: tlb_way_tags_t) return tlb_tag_t is |
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variable j : integer; |
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begin |
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if TLB_NUM_WAYS = 1 then |
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return tags; |
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else |
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j := way * TLB_EA_TAG_BITS; |
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return tags(j + TLB_EA_TAG_BITS - 1 downto j); |
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end if; |
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end; |
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-- Write a TLB tag to a TLB tag memory row |
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@ -449,23 +453,35 @@ architecture rtl of dcache is
@@ -449,23 +453,35 @@ architecture rtl of dcache is
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tag: tlb_tag_t) is |
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variable j : integer; |
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begin |
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if TLB_NUM_WAYS = 1 then |
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tags := tag; |
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else |
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j := way * TLB_EA_TAG_BITS; |
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tags(j + TLB_EA_TAG_BITS - 1 downto j) := tag; |
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end if; |
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end; |
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-- Read a PTE from a TLB PTE memory row |
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function read_tlb_pte(way: tlb_way_t; ptes: tlb_way_ptes_t) return tlb_pte_t is |
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variable j : integer; |
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begin |
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if TLB_NUM_WAYS = 1 then |
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return ptes; |
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else |
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j := way * TLB_PTE_BITS; |
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return ptes(j + TLB_PTE_BITS - 1 downto j); |
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end if; |
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end; |
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procedure write_tlb_pte(way: tlb_way_t; ptes: inout tlb_way_ptes_t; newpte: tlb_pte_t) is |
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variable j : integer; |
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begin |
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if TLB_NUM_WAYS = 1 then |
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ptes := newpte; |
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else |
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j := way * TLB_PTE_BITS; |
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ptes(j + TLB_PTE_BITS - 1 downto j) := newpte; |
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end if; |
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end; |
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begin |
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