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master
fpu-init
loadstore-init
core_debug-init
icache-unused-sig
icache-insn-u-state
dcache-unused-sig
unused-sig
divider-init
loadstore-pmu-init
icache-pmu-events
fpu-typo
less-fpga-init
caravel-mpw6-20220530
caravel-mpw5-20220323
caravel-mpw5-20220322
alt-reset-address
log2ceil-issue
fpu-constant
asic-3
boxarty-20211011
icbi-issue
orange-crab-freq
dcache-nc-fix
remove-potato-uart
cache-tlb-parameters-2
caravel-20210114
caravel-20210105
jtag-port-2
jtag-port
nia-debug
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microwatt/scripts
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Benjamin Herrenschmidt b557ec3a05 mw_debug: Default to jtag backend if unspecified 
It avoids typing it all the time

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 		3 years ago
..
fmt_log decode: Add a facility field to the instruction decode tables 3 years ago
mw_debug mw_debug: Default to jtag backend if unspecified 3 years ago
bin2hex.py bin2hex: Make sure to generate little endian files 4 years ago
dependencies.py uart: Rename sim_uart.vhdl to sim_pp_uart.vhdl 4 years ago
gen_icache_tb.py icache_tb: Improve test and include test file 5 years ago
run_test.sh Dump CTR, LR and CR on sim termination, and update our tests 4 years ago
run_test_console.sh Add test cases for new exceptions and supervisor state 4 years ago
test_micropython.py Update micropython 4 years ago
test_micropython_long.py Update micropython 4 years ago
test_micropython_verilator.py makefile: Add some verilator micropython tests 3 years ago
test_micropython_verilator_long.py makefile: Add some verilator micropython tests 3 years ago
vhdltags Add VHDL TAGS 4 years ago