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17d533219b
The verilator simulation interface uses the remote_bitbang protocol from openocd. I have a simple implementation for urjtag too. Signed-off-by: Anton Blanchard <anton@linux.ibm.com> |
4 years ago | |
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LICENSE | 5 years ago | |
acorn-cle-215.xdc | 4 years ago | |
arty_a7.xdc | 4 years ago | |
clk_gen_bypass.vhd | 5 years ago | |
clk_gen_ecp5.vhd | 4 years ago | |
clk_gen_mcmm.vhd | 5 years ago | |
clk_gen_plle2.vhd | 4 years ago | |
cmod_a7-35.xdc | 5 years ago | |
firmware.hex | 5 years ago | |
fpga-random.vhdl | 4 years ago | |
fpga-random.xdc | 4 years ago | |
genesys2.xdc | 4 years ago | |
hello_world.hex | 5 years ago | |
main_bram.vhdl | 5 years ago | |
nexys-video.xdc | 5 years ago | |
nexys_a7.xdc | 5 years ago | |
pp_fifo.vhd | 5 years ago | |
pp_soc_uart.vhd | 5 years ago | |
pp_utilities.vhd | 5 years ago | |
soc_reset.vhdl | 5 years ago | |
soc_reset_tb.vhdl | 5 years ago | |
top-acorn-cle-215.vhdl | 4 years ago | |
top-arty.vhdl | 4 years ago | |
top-generic.vhdl | 4 years ago | |
top-genesys2.vhdl | 4 years ago | |
top-nexys-video.vhdl | 4 years ago |