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microwatt/litedram/extras
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Benjamin Herrenschmidt 02abb135a8 litedram: l2: Add support for more geometries 
Make the DRAM data lines and user port width configurable, also
don't hard wire dependency on the wishbone data width.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 		5 years ago
..
fusesoc-add-files.py litedram: Remove old "VexRiscV" based initializations 5 years ago
litedram-wrapper-l2.vhdl litedram: l2: Add support for more geometries 5 years ago
sim_dram_verilate.mk litedram: Add simulation support 5 years ago
sim_litedram.vhdl litedram: Add simulation support 5 years ago
sim_litedram_c.cpp litedram: Add simulation support 5 years ago
wave.gtkw litedram: Add an L2 cache with store queue 5 years ago
wave.opt litedram: Add an L2 cache with store queue 5 years ago
wave_tb.gtkw litedram: l2: Latency improvements 5 years ago