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02abb135a8
Make the DRAM data lines and user port width configurable, also don't hard wire dependency on the wishbone data width. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> |
5 years ago | |
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fusesoc-add-files.py | 5 years ago | |
litedram-wrapper-l2.vhdl | 5 years ago | |
sim_dram_verilate.mk | 5 years ago | |
sim_litedram.vhdl | 5 years ago | |
sim_litedram_c.cpp | 5 years ago | |
wave.gtkw | 5 years ago | |
wave.opt | 5 years ago | |
wave_tb.gtkw | 5 years ago |