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microwatt/fpga
Benjamin Herrenschmidt e5aa0e9dc9 uart: Remove combinational loops on ack and stall signal
They hurt timing forcing signals to come from the master and back
again in one cycle. Stall isn't sampled by the master unless there
is an active cycle so masking it with cyc is pointless. Masking acks
is somewhat pointless too as we don't handle early dropping of cyc
in any of our slaves properly anyways.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
..
LICENSE
arty_a7.xdc spi: Add SPI Flash controller 5 years ago
clk_gen_bypass.vhd
clk_gen_mcmm.vhd
clk_gen_plle2.vhd
cmod_a7-35.xdc
firmware.hex
hello_world.hex hello_world: Use new headers and frequency from syscon 5 years ago
main_bram.vhdl
nexys-video.xdc spi: Add SPI Flash controller 5 years ago
nexys_a7.xdc
pp_fifo.vhd pp_fifo: Fix full fifo losing all data on simultaneous push & pop 5 years ago
pp_soc_uart.vhd uart: Remove combinational loops on ack and stall signal 5 years ago
pp_utilities.vhd
soc_reset.vhdl soc_reset: Use counters, add synchronizers 5 years ago
soc_reset_tb.vhdl Exit cleanly from testbench on success 5 years ago
top-arty.vhdl spi: Add SPI Flash controller 5 years ago
top-generic.vhdl spi: Add SPI Flash controller 5 years ago
top-nexys-video.vhdl spi: Add SPI Flash controller 5 years ago