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Michael Neuling
d7458d5beb
The icache RAM is currently LUT ram not block ram. This massively bloats the icache size. We think this is due to yosys not inferencing the RAM correctly but that's yet to be confirmed. Work around this for now by reducing the default size of the icache RAM for the ECP5 builds. On the ECP5 85K builts, this gets us from 95% down to 76% and helps our CI to pass. Signed-off-by: Michael Neuling <mikey@neuling.org> |
3 years ago | |
|---|---|---|
| .. | ||
| LICENSE | 5 years ago | |
| acorn-cle-215.xdc | 4 years ago | |
| arty_a7.xdc | 3 years ago | |
| clk_gen_bypass.vhd | 5 years ago | |
| clk_gen_ecp5.vhd | 4 years ago | |
| clk_gen_mcmm.vhd | 5 years ago | |
| clk_gen_plle2.vhd | 4 years ago | |
| cmod_a7-35.xdc | 4 years ago | |
| firmware.hex | 5 years ago | |
| fpga-random.vhdl | 4 years ago | |
| fpga-random.xdc | 4 years ago | |
| genesys2.xdc | 4 years ago | |
| hello_world.hex | 4 years ago | |
| main_bram.vhdl | 4 years ago | |
| nexys-video.xdc | 4 years ago | |
| nexys_a7.xdc | 4 years ago | |
| pp_fifo.vhd | 4 years ago | |
| pp_soc_uart.vhd | 4 years ago | |
| pp_utilities.vhd | 5 years ago | |
| soc_reset.vhdl | 4 years ago | |
| soc_reset_tb.vhdl | 4 years ago | |
| top-acorn-cle-215.vhdl | 4 years ago | |
| top-arty.vhdl | 3 years ago | |
| top-generic.vhdl | 3 years ago | |
| top-genesys2.vhdl | 4 years ago | |
| top-nexys-video.vhdl | 3 years ago | |