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114 lines
3.9 KiB
VHDL
114 lines
3.9 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.wishbone_types.all;
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entity toplevel is
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generic (
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MEMORY_SIZE : integer := 8192;
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RAM_INIT_FILE : string := "firmware.hex";
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RESET_LOW : boolean := true;
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CLK_INPUT : positive := 100000000;
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CLK_FREQUENCY : positive := 100000000;
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HAS_FPU : boolean := true;
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HAS_BTC : boolean := false;
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NO_BRAM : boolean := false;
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DISABLE_FLATTEN_CORE : boolean := false;
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SPI_FLASH_OFFSET : integer := 0;
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SPI_FLASH_DEF_CKDV : natural := 4;
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SPI_FLASH_DEF_QUAD : boolean := false;
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SPI_BOOT_CLOCKS : boolean := false;
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LOG_LENGTH : natural := 0;
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UART_IS_16550 : boolean := true;
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HAS_UART1 : boolean := false;
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ICACHE_NUM_LINES : natural := 4;
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ICACHE_NUM_WAYS : natural := 2;
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ICACHE_TLB_SIZE : natural := 4;
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DCACHE_NUM_LINES : natural := 4;
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DCACHE_NUM_WAYS : natural := 2;
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DCACHE_TLB_SET_SIZE : natural := 2;
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DCACHE_TLB_NUM_WAYS : natural := 2
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);
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port(
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ext_clk : in std_ulogic;
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ext_rst : in std_ulogic;
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-- UART0 signals:
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uart0_txd : out std_ulogic;
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uart0_rxd : in std_ulogic;
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-- UART1 signals:
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uart1_txd : out std_ulogic;
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uart1_rxd : in std_ulogic;
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-- SPI
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spi_flash_cs_n : out std_ulogic;
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spi_flash_clk : out std_ulogic;
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spi_flash_sdat_i : in std_ulogic_vector(3 downto 0);
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spi_flash_sdat_o : out std_ulogic_vector(3 downto 0);
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spi_flash_sdat_oe : out std_ulogic_vector(3 downto 0)
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);
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end entity toplevel;
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architecture behaviour of toplevel is
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-- reset signals
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signal system_rst : std_ulogic;
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begin
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system_rst <= not ext_rst when RESET_LOW else ext_rst;
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-- Main SoC
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soc0: entity work.soc
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generic map(
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MEMORY_SIZE => MEMORY_SIZE,
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RAM_INIT_FILE => RAM_INIT_FILE,
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SIM => false,
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CLK_FREQ => CLK_FREQUENCY,
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HAS_FPU => HAS_FPU,
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HAS_BTC => HAS_BTC,
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HAS_DRAM => false,
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DRAM_SIZE => 0,
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DRAM_INIT_SIZE => 0,
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DISABLE_FLATTEN_CORE => DISABLE_FLATTEN_CORE,
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HAS_SPI_FLASH => true,
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SPI_FLASH_DLINES => 4,
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SPI_FLASH_OFFSET => SPI_FLASH_OFFSET,
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SPI_FLASH_DEF_CKDV => SPI_FLASH_DEF_CKDV,
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SPI_FLASH_DEF_QUAD => SPI_FLASH_DEF_QUAD,
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SPI_BOOT_CLOCKS => SPI_BOOT_CLOCKS,
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LOG_LENGTH => LOG_LENGTH,
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UART0_IS_16550 => UART_IS_16550,
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HAS_UART1 => HAS_UART1,
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ICACHE_NUM_LINES => ICACHE_NUM_LINES,
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ICACHE_NUM_WAYS => ICACHE_NUM_WAYS,
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ICACHE_TLB_SIZE => ICACHE_TLB_SIZE,
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DCACHE_NUM_LINES => DCACHE_NUM_LINES,
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DCACHE_NUM_WAYS => DCACHE_NUM_WAYS,
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DCACHE_TLB_SET_SIZE => DCACHE_TLB_SET_SIZE,
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DCACHE_TLB_NUM_WAYS => DCACHE_TLB_NUM_WAYS
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)
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port map (
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-- System signals
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system_clk => ext_clk,
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rst => system_rst,
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-- UART signals
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uart0_txd => uart0_txd,
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uart0_rxd => uart0_rxd,
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-- UART1 signals
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uart1_txd => uart1_txd,
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uart1_rxd => uart1_rxd,
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-- SPI signals
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spi_flash_sck => spi_flash_clk,
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spi_flash_cs_n => spi_flash_cs_n,
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spi_flash_sdat_o => spi_flash_sdat_o,
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spi_flash_sdat_oe => spi_flash_sdat_oe,
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spi_flash_sdat_i => spi_flash_sdat_i
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);
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end architecture behaviour;
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