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microwatt/litedram
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Benjamin Herrenschmidt 1441b2a859 litedram: l2: Latency improvements 
This implements in the L2 cache the feature already in the L1s
allowing a request to be completed before the end of a refill
using partial line valid bits, and starting a refill from the
row of the first miss on that line instead of the beginning of
the line.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 		4 years ago
..
extras litedram: l2: Latency improvements 4 years ago
gen-src Merge pull request #213 from ozbenh/uart16550 4 years ago
generated console: Add support for the 16550 UART 4 years ago
litedram.core litedram: Add basic support for LiteX LiteDRAM 5 years ago