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microwatt/fpga
Benjamin Herrenschmidt 5ae5f76558 arty/nexys-video: Update XDC
The DRAM related pins have some small changes in LiteX, so resync
and add the false path information as well.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
..
LICENSE
arty_a7.xdc arty/nexys-video: Update XDC 4 years ago
clk_gen_bypass.vhd Fix clk_gen_bypass 5 years ago
clk_gen_mcmm.vhd Improve PLL/MMCM clocks configuration 5 years ago
clk_gen_plle2.vhd Improve PLL/MMCM clocks configuration 5 years ago
cmod_a7-35.xdc Add SPI configuration to Xilinx constraint files 5 years ago
firmware.hex Add a few more FPGA related files 5 years ago
hello_world.hex hello_world: Use new headers and frequency from syscon 5 years ago
main_bram.vhdl Fix some ghdlsynth issues with fpga_bram 5 years ago
nexys-video.xdc arty/nexys-video: Update XDC 4 years ago
nexys_a7.xdc Add SPI configuration to Xilinx constraint files 5 years ago
pp_fifo.vhd pp_fifo: Fix full fifo losing all data on simultaneous push & pop 5 years ago
pp_soc_uart.vhd pp_soc_uart: Fix rx synchronizers and ensure stable tx init state 5 years ago
pp_utilities.vhd
soc_reset.vhdl soc_reset: Use counters, add synchronizers 5 years ago
soc_reset_tb.vhdl Exit cleanly from testbench on success 5 years ago
top-arty.vhdl litedram: Remove remnants of riscv-inits 4 years ago
top-generic.vhdl soc: Rework interconnect 5 years ago
top-nexys-video.vhdl litedram: Remove remnants of riscv-inits 4 years ago