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119 lines
3.8 KiB
VHDL
119 lines
3.8 KiB
VHDL
-- Sim console UART, provides the same interface as potato UART by
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-- Kristian Klomsten Skordal.
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.wishbone_types.all;
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use work.sim_console.all;
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--! @brief Simple UART module.
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--! The following registers are defined:
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--! |--------------------|--------------------------------------------|
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--! | Address | Description |
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--! |--------------------|--------------------------------------------|
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--! | 0x00 | Transmit register (write-only) |
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--! | 0x08 | Receive register (read-only) |
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--! | 0x10 | Status register (read-only) |
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--! | 0x18 | Sample clock divisor register (dummy) |
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--! | 0x20 | Interrupt enable register (read/write) |
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--! |--------------------|--------------------------------------------|
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--!
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--! The status register contains the following bits:
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--! - Bit 0: receive buffer empty
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--! - Bit 1: transmit buffer empty
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--! - Bit 2: receive buffer full
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--! - Bit 3: transmit buffer full
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--!
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--! Interrupts are enabled by setting the corresponding bit in the interrupt
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--! enable register. The following bits are available:
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--! - Bit 0: data received (receive buffer not empty)
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--! - Bit 1: ready to send data (transmit buffer empty)
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entity sim_uart is
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port(
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clk : in std_logic;
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reset : in std_logic;
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-- Wishbone ports:
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wishbone_in : in wishbone_master_out;
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wishbone_out : out wishbone_slave_out
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);
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end entity sim_uart;
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architecture behaviour of sim_uart is
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signal sample_clk_divisor : std_logic_vector(7 downto 0);
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-- IRQ enable signals:
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signal irq_recv_enable, irq_tx_ready_enable : std_logic := '0';
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-- Wishbone signals:
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type wb_state_type is (IDLE, WRITE_ACK, READ_ACK);
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signal wb_state : wb_state_type;
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signal wb_ack : std_logic; --! Wishbone acknowledge signal
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begin
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wishbone_out.ack <= wb_ack and wishbone_in.cyc and wishbone_in.stb;
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wishbone: process(clk)
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variable sim_tmp : std_logic_vector(63 downto 0);
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begin
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if rising_edge(clk) then
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if reset = '1' then
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wb_ack <= '0';
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wb_state <= IDLE;
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sample_clk_divisor <= (others => '0');
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irq_recv_enable <= '0';
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irq_tx_ready_enable <= '0';
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else
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case wb_state is
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when IDLE =>
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if wishbone_in.cyc = '1' and wishbone_in.stb = '1' then
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if wishbone_in.we = '1' then -- Write to register
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if wishbone_in.adr(11 downto 0) = x"000" then
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report "FOO !";
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sim_console_write(wishbone_in.dat);
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elsif wishbone_in.adr(11 downto 0) = x"018" then
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sample_clk_divisor <= wishbone_in.dat(7 downto 0);
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elsif wishbone_in.adr(11 downto 0) = x"020" then
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irq_recv_enable <= wishbone_in.dat(0);
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irq_tx_ready_enable <= wishbone_in.dat(1);
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end if;
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wb_ack <= '1';
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wb_state <= WRITE_ACK;
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else -- Read from register
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if wishbone_in.adr(11 downto 0) = x"008" then
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sim_console_read(sim_tmp);
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wishbone_out.dat <= sim_tmp;
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elsif wishbone_in.adr(11 downto 0) = x"010" then
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sim_console_poll(sim_tmp);
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wishbone_out.dat <= x"000000000000000" & '0' &
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sim_tmp(0) & '1' & not sim_tmp(0);
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elsif wishbone_in.adr(11 downto 0) = x"018" then
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wishbone_out.dat <= x"00000000000000" & sample_clk_divisor;
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elsif wishbone_in.adr(11 downto 0) = x"020" then
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wishbone_out.dat <= (0 => irq_recv_enable,
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1 => irq_tx_ready_enable,
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others => '0');
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else
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wishbone_out.dat <= (others => '0');
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end if;
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wb_ack <= '1';
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wb_state <= READ_ACK;
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end if;
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end if;
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when WRITE_ACK|READ_ACK =>
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if wishbone_in.stb = '0' then
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wb_ack <= '0';
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wb_state <= IDLE;
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end if;
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end case;
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end if;
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end if;
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end process wishbone;
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end architecture behaviour;
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