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microwatt/fpga
Benjamin Herrenschmidt b0241d9f2d corefile/nexys_video: Parameter fixes
This fixes up a few issues with parameters:

Only arty has "has_uart1" since we haven't added plumbing for a second UART
anywhere else. Also "uart_is_16550" was mixing on one of the nexys_video
targets, and nexys_video toplevel was missing LOG_LENGTH.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
..
LICENSE
arty_a7.xdc uart: Import and hook up opencore 16550 compatible UART 4 years ago
clk_gen_bypass.vhd Fix clk_gen_bypass 5 years ago
clk_gen_ecp5.vhd Add PLL for ECP5 device 4 years ago
clk_gen_mcmm.vhd Improve PLL/MMCM clocks configuration 5 years ago
clk_gen_plle2.vhd Improve PLL/MMCM clocks configuration 5 years ago
cmod_a7-35.xdc Add SPI configuration to Xilinx constraint files 5 years ago
firmware.hex Add a few more FPGA related files 5 years ago
hello_world.hex hello_world: Use new headers and frequency from syscon 5 years ago
main_bram.vhdl Fix some ghdlsynth issues with fpga_bram 5 years ago
nexys-video.xdc spi: Add SPI Flash controller 5 years ago
nexys_a7.xdc Add SPI configuration to Xilinx constraint files 5 years ago
pp_fifo.vhd pp_fifo: Fix full fifo losing all data on simultaneous push & pop 5 years ago
pp_soc_uart.vhd uart: Remove combinational loops on ack and stall signal 5 years ago
pp_utilities.vhd
soc_reset.vhdl soc_reset: Use counters, add synchronizers 5 years ago
soc_reset_tb.vhdl Exit cleanly from testbench on success 5 years ago
top-arty.vhdl uart: Make 16550 the default 4 years ago
top-generic.vhdl uart: Make 16550 the default 4 years ago
top-nexys-video.vhdl corefile/nexys_video: Parameter fixes 4 years ago