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025cf5efe8
These provides some info about the SoC (though it's still somewhat incomplete and needs more work, see comments). There's also a control register for selecting DRAM vs. BRAM at 0 (and for soft-resetting the SoC but that isn't wired up yet). Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> |
5 years ago | |
|---|---|---|
| .. | ||
| sdram_init | 5 years ago | |
| arty.yml | 5 years ago | |
| generate.py | 5 years ago | |
| nexys-video.yml | 5 years ago | |
| wrapper-mw-init.vhdl | 5 years ago | |
| wrapper-self-init.vhdl | 5 years ago | |