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68 lines
1.3 KiB
VHDL
68 lines
1.3 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.common.all;
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entity fetch1 is
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generic(
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RESET_ADDRESS : std_logic_vector(63 downto 0) := (others => '0')
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);
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port(
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clk : in std_ulogic;
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rst : in std_ulogic;
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-- Control inputs:
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stall_in : in std_ulogic;
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flush_in : in std_ulogic;
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-- redirect from execution unit
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e_in : in Execute1ToFetch1Type;
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-- fetch data out
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f_out : out Fetch1ToFetch2Type
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);
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end entity fetch1;
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architecture behaviour of fetch1 is
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signal r, r_next : Fetch1ToFetch2Type;
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begin
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regs : process(clk)
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begin
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if rising_edge(clk) then
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if rst = '1' or e_in.redirect = '1' or stall_in = '0' then
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r <= r_next;
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end if;
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end if;
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end process;
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comb : process(all)
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variable v : Fetch1ToFetch2Type;
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begin
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v := r;
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if rst = '1' then
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v.nia := RESET_ADDRESS;
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elsif e_in.redirect = '1' then
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v.nia := e_in.redirect_nia;
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else
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v.nia := std_logic_vector(unsigned(v.nia) + 4);
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end if;
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r_next <= v;
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-- Update outputs to the icache
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f_out <= r;
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report "fetch1 rst:" & std_ulogic'image(rst) &
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" R:" & std_ulogic'image(e_in.redirect) &
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" S:" & std_ulogic'image(stall_in) &
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" nia_next:" & to_hstring(r_next.nia) &
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" nia:" & to_hstring(r.nia);
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end process;
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end architecture behaviour;
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