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3811 lines
203 KiB
Verilog
3811 lines
203 KiB
Verilog
//--------------------------------------------------------------------------------
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// Auto-generated by Migen (a5bc262) & LiteX (de028765) on 2021-09-24 12:37:01
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//--------------------------------------------------------------------------------
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module liteeth_core(
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input wire sys_clock,
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input wire sys_reset,
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input wire gmii_eth_clocks_tx,
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output wire gmii_eth_clocks_gtx,
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input wire gmii_eth_clocks_rx,
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output wire gmii_eth_rst_n,
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input wire gmii_eth_int_n,
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inout wire gmii_eth_mdio,
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output wire gmii_eth_mdc,
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input wire gmii_eth_rx_dv,
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input wire gmii_eth_rx_er,
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input wire [7:0] gmii_eth_rx_data,
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output reg gmii_eth_tx_en,
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output wire gmii_eth_tx_er,
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output reg [7:0] gmii_eth_tx_data,
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input wire gmii_eth_col,
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input wire gmii_eth_crs,
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input wire [29:0] wishbone_adr,
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input wire [31:0] wishbone_dat_w,
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output wire [31:0] wishbone_dat_r,
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input wire [3:0] wishbone_sel,
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input wire wishbone_cyc,
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input wire wishbone_stb,
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output wire wishbone_ack,
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input wire wishbone_we,
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input wire [2:0] wishbone_cti,
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input wire [1:0] wishbone_bte,
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output wire wishbone_err,
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output wire interrupt
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);
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reg maccore_maccore_soc_rst = 1'd0;
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wire maccore_maccore_cpu_rst;
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reg [1:0] maccore_maccore_reset_storage = 2'd0;
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reg maccore_maccore_reset_re = 1'd0;
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reg [31:0] maccore_maccore_scratch_storage = 32'd305419896;
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reg maccore_maccore_scratch_re = 1'd0;
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wire [31:0] maccore_maccore_bus_errors_status;
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wire maccore_maccore_bus_errors_we;
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reg maccore_maccore_bus_errors_re = 1'd0;
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wire maccore_maccore_bus_error;
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reg [31:0] maccore_maccore_bus_errors = 32'd0;
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(* dont_touch = "true" *) wire sys_clk;
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wire sys_rst;
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wire por_clk;
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reg maccore_int_rst = 1'd1;
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reg maccore_ethphy_mode0 = 1'd0;
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wire maccore_ethphy_mode_status;
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wire maccore_ethphy_mode_we;
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reg maccore_ethphy_mode_re = 1'd0;
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reg maccore_ethphy_mode1 = 1'd0;
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reg maccore_ethphy_update_mode = 1'd0;
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wire maccore_ethphy_eth_tick;
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reg [9:0] maccore_ethphy_eth_counter = 10'd0;
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wire maccore_ethphy_sys_tick;
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wire maccore_ethphy_i;
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wire maccore_ethphy_o;
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reg maccore_ethphy_toggle_i = 1'd0;
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wire maccore_ethphy_toggle_o;
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reg maccore_ethphy_toggle_o_r = 1'd0;
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reg [23:0] maccore_ethphy_sys_counter = 24'd0;
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reg maccore_ethphy_sys_counter_reset = 1'd0;
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reg maccore_ethphy_sys_counter_ce = 1'd0;
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reg maccore_ethphy_reset_storage = 1'd0;
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reg maccore_ethphy_reset_re = 1'd0;
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(* dont_touch = "true" *) wire eth_rx_clk;
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wire eth_rx_rst;
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(* dont_touch = "true" *) wire eth_tx_clk;
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wire eth_tx_rst;
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reg maccore_ethphy_eth_tx_clk = 1'd0;
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wire maccore_ethphy_reset0;
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wire maccore_ethphy_reset1;
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reg [8:0] maccore_ethphy_counter = 9'd0;
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wire maccore_ethphy_counter_done;
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wire maccore_ethphy_counter_ce;
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wire maccore_ethphy_liteethphygmiimiitx_sink_sink_valid0;
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wire maccore_ethphy_liteethphygmiimiitx_sink_sink_ready0;
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wire maccore_ethphy_liteethphygmiimiitx_sink_sink_first0;
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wire maccore_ethphy_liteethphygmiimiitx_sink_sink_last0;
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wire [7:0] maccore_ethphy_liteethphygmiimiitx_sink_sink_payload_data0;
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wire maccore_ethphy_liteethphygmiimiitx_sink_sink_payload_last_be0;
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wire maccore_ethphy_liteethphygmiimiitx_sink_sink_payload_error0;
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reg maccore_ethphy_liteethphygmiimiitx_gmii_tx_pads_tx_er = 1'd0;
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reg maccore_ethphy_liteethphygmiimiitx_gmii_tx_pads_tx_en = 1'd0;
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reg [7:0] maccore_ethphy_liteethphygmiimiitx_gmii_tx_pads_tx_data = 8'd0;
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wire maccore_ethphy_liteethphygmiimiitx_gmii_tx_sink_valid;
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reg maccore_ethphy_liteethphygmiimiitx_gmii_tx_sink_ready = 1'd0;
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wire maccore_ethphy_liteethphygmiimiitx_gmii_tx_sink_first;
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wire maccore_ethphy_liteethphygmiimiitx_gmii_tx_sink_last;
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wire [7:0] maccore_ethphy_liteethphygmiimiitx_gmii_tx_sink_payload_data;
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wire maccore_ethphy_liteethphygmiimiitx_gmii_tx_sink_payload_last_be;
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wire maccore_ethphy_liteethphygmiimiitx_gmii_tx_sink_payload_error;
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reg maccore_ethphy_liteethphygmiimiitx_mii_tx_pads_tx_er = 1'd0;
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reg maccore_ethphy_liteethphygmiimiitx_mii_tx_pads_tx_en = 1'd0;
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reg [7:0] maccore_ethphy_liteethphygmiimiitx_mii_tx_pads_tx_data = 8'd0;
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wire maccore_ethphy_liteethphygmiimiitx_sink_sink_valid1;
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wire maccore_ethphy_liteethphygmiimiitx_sink_sink_ready1;
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wire maccore_ethphy_liteethphygmiimiitx_sink_sink_first1;
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wire maccore_ethphy_liteethphygmiimiitx_sink_sink_last1;
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wire [7:0] maccore_ethphy_liteethphygmiimiitx_sink_sink_payload_data1;
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wire maccore_ethphy_liteethphygmiimiitx_sink_sink_payload_last_be1;
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wire maccore_ethphy_liteethphygmiimiitx_sink_sink_payload_error1;
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wire maccore_ethphy_liteethphygmiimiitx_converter_sink_valid;
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wire maccore_ethphy_liteethphygmiimiitx_converter_sink_ready;
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reg maccore_ethphy_liteethphygmiimiitx_converter_sink_first = 1'd0;
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reg maccore_ethphy_liteethphygmiimiitx_converter_sink_last = 1'd0;
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wire [7:0] maccore_ethphy_liteethphygmiimiitx_converter_sink_payload_data;
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wire maccore_ethphy_liteethphygmiimiitx_converter_source_valid;
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wire maccore_ethphy_liteethphygmiimiitx_converter_source_ready;
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wire maccore_ethphy_liteethphygmiimiitx_converter_source_first;
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wire maccore_ethphy_liteethphygmiimiitx_converter_source_last;
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wire [3:0] maccore_ethphy_liteethphygmiimiitx_converter_source_payload_data;
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wire maccore_ethphy_liteethphygmiimiitx_converter_converter_sink_valid;
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wire maccore_ethphy_liteethphygmiimiitx_converter_converter_sink_ready;
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wire maccore_ethphy_liteethphygmiimiitx_converter_converter_sink_first;
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wire maccore_ethphy_liteethphygmiimiitx_converter_converter_sink_last;
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reg [7:0] maccore_ethphy_liteethphygmiimiitx_converter_converter_sink_payload_data = 8'd0;
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wire maccore_ethphy_liteethphygmiimiitx_converter_converter_source_valid;
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wire maccore_ethphy_liteethphygmiimiitx_converter_converter_source_ready;
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wire maccore_ethphy_liteethphygmiimiitx_converter_converter_source_first;
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wire maccore_ethphy_liteethphygmiimiitx_converter_converter_source_last;
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reg [3:0] maccore_ethphy_liteethphygmiimiitx_converter_converter_source_payload_data = 4'd0;
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wire maccore_ethphy_liteethphygmiimiitx_converter_converter_source_payload_valid_token_count;
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reg maccore_ethphy_liteethphygmiimiitx_converter_converter_mux = 1'd0;
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wire maccore_ethphy_liteethphygmiimiitx_converter_converter_first;
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wire maccore_ethphy_liteethphygmiimiitx_converter_converter_last;
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wire maccore_ethphy_liteethphygmiimiitx_converter_source_source_valid;
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wire maccore_ethphy_liteethphygmiimiitx_converter_source_source_ready;
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wire maccore_ethphy_liteethphygmiimiitx_converter_source_source_first;
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wire maccore_ethphy_liteethphygmiimiitx_converter_source_source_last;
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wire [3:0] maccore_ethphy_liteethphygmiimiitx_converter_source_source_payload_data;
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wire maccore_ethphy_liteethphygmiimiitx_demux_sink_valid;
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reg maccore_ethphy_liteethphygmiimiitx_demux_sink_ready = 1'd0;
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wire maccore_ethphy_liteethphygmiimiitx_demux_sink_first;
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wire maccore_ethphy_liteethphygmiimiitx_demux_sink_last;
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wire [7:0] maccore_ethphy_liteethphygmiimiitx_demux_sink_payload_data;
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wire maccore_ethphy_liteethphygmiimiitx_demux_sink_payload_last_be;
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wire maccore_ethphy_liteethphygmiimiitx_demux_sink_payload_error;
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reg maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_valid = 1'd0;
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wire maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_ready;
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reg maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_first = 1'd0;
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reg maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_last = 1'd0;
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reg [7:0] maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_payload_data = 8'd0;
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reg maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_payload_last_be = 1'd0;
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reg maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_payload_error = 1'd0;
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reg maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_valid = 1'd0;
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wire maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_ready;
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reg maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_first = 1'd0;
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reg maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_last = 1'd0;
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reg [7:0] maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_payload_data = 8'd0;
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reg maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_payload_last_be = 1'd0;
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reg maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_payload_error = 1'd0;
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wire maccore_ethphy_liteethphygmiimiitx_demux_sel;
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wire maccore_ethphy_liteethphygmiimiirx_source_source_valid0;
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wire maccore_ethphy_liteethphygmiimiirx_source_source_ready0;
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wire maccore_ethphy_liteethphygmiimiirx_source_source_first0;
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wire maccore_ethphy_liteethphygmiimiirx_source_source_last0;
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wire [7:0] maccore_ethphy_liteethphygmiimiirx_source_source_payload_data0;
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wire maccore_ethphy_liteethphygmiimiirx_source_source_payload_last_be0;
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wire maccore_ethphy_liteethphygmiimiirx_source_source_payload_error0;
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reg maccore_ethphy_liteethphygmiimiirx_pads_d_rx_dv = 1'd0;
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reg [7:0] maccore_ethphy_liteethphygmiimiirx_pads_d_rx_data = 8'd0;
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reg maccore_ethphy_liteethphygmiimiirx_gmii_rx_source_valid = 1'd0;
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wire maccore_ethphy_liteethphygmiimiirx_gmii_rx_source_ready;
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reg maccore_ethphy_liteethphygmiimiirx_gmii_rx_source_first = 1'd0;
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wire maccore_ethphy_liteethphygmiimiirx_gmii_rx_source_last;
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reg [7:0] maccore_ethphy_liteethphygmiimiirx_gmii_rx_source_payload_data = 8'd0;
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reg maccore_ethphy_liteethphygmiimiirx_gmii_rx_source_payload_last_be = 1'd0;
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reg maccore_ethphy_liteethphygmiimiirx_gmii_rx_source_payload_error = 1'd0;
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reg maccore_ethphy_liteethphygmiimiirx_gmii_rx_dv_d = 1'd0;
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wire maccore_ethphy_liteethphygmiimiirx_source_source_valid1;
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wire maccore_ethphy_liteethphygmiimiirx_source_source_ready1;
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wire maccore_ethphy_liteethphygmiimiirx_source_source_first1;
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wire maccore_ethphy_liteethphygmiimiirx_source_source_last1;
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wire [7:0] maccore_ethphy_liteethphygmiimiirx_source_source_payload_data1;
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reg maccore_ethphy_liteethphygmiimiirx_source_source_payload_last_be1 = 1'd0;
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reg maccore_ethphy_liteethphygmiimiirx_source_source_payload_error1 = 1'd0;
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reg maccore_ethphy_liteethphygmiimiirx_converter_sink_valid = 1'd0;
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wire maccore_ethphy_liteethphygmiimiirx_converter_sink_ready;
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reg maccore_ethphy_liteethphygmiimiirx_converter_sink_first = 1'd0;
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wire maccore_ethphy_liteethphygmiimiirx_converter_sink_last;
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reg [3:0] maccore_ethphy_liteethphygmiimiirx_converter_sink_payload_data = 4'd0;
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wire maccore_ethphy_liteethphygmiimiirx_converter_source_valid;
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wire maccore_ethphy_liteethphygmiimiirx_converter_source_ready;
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wire maccore_ethphy_liteethphygmiimiirx_converter_source_first;
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wire maccore_ethphy_liteethphygmiimiirx_converter_source_last;
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reg [7:0] maccore_ethphy_liteethphygmiimiirx_converter_source_payload_data = 8'd0;
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wire maccore_ethphy_liteethphygmiimiirx_converter_converter_sink_valid;
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wire maccore_ethphy_liteethphygmiimiirx_converter_converter_sink_ready;
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wire maccore_ethphy_liteethphygmiimiirx_converter_converter_sink_first;
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wire maccore_ethphy_liteethphygmiimiirx_converter_converter_sink_last;
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wire [3:0] maccore_ethphy_liteethphygmiimiirx_converter_converter_sink_payload_data;
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wire maccore_ethphy_liteethphygmiimiirx_converter_converter_source_valid;
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wire maccore_ethphy_liteethphygmiimiirx_converter_converter_source_ready;
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reg maccore_ethphy_liteethphygmiimiirx_converter_converter_source_first = 1'd0;
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reg maccore_ethphy_liteethphygmiimiirx_converter_converter_source_last = 1'd0;
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reg [7:0] maccore_ethphy_liteethphygmiimiirx_converter_converter_source_payload_data = 8'd0;
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reg [1:0] maccore_ethphy_liteethphygmiimiirx_converter_converter_source_payload_valid_token_count = 2'd0;
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reg maccore_ethphy_liteethphygmiimiirx_converter_converter_demux = 1'd0;
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wire maccore_ethphy_liteethphygmiimiirx_converter_converter_load_part;
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reg maccore_ethphy_liteethphygmiimiirx_converter_converter_strobe_all = 1'd0;
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wire maccore_ethphy_liteethphygmiimiirx_converter_source_source_valid;
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wire maccore_ethphy_liteethphygmiimiirx_converter_source_source_ready;
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wire maccore_ethphy_liteethphygmiimiirx_converter_source_source_first;
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wire maccore_ethphy_liteethphygmiimiirx_converter_source_source_last;
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wire [7:0] maccore_ethphy_liteethphygmiimiirx_converter_source_source_payload_data;
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reg maccore_ethphy_liteethphygmiimiirx_converter_reset = 1'd0;
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reg maccore_ethphy_liteethphygmiimiirx_mux_source_valid = 1'd0;
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wire maccore_ethphy_liteethphygmiimiirx_mux_source_ready;
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reg maccore_ethphy_liteethphygmiimiirx_mux_source_first = 1'd0;
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reg maccore_ethphy_liteethphygmiimiirx_mux_source_last = 1'd0;
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reg [7:0] maccore_ethphy_liteethphygmiimiirx_mux_source_payload_data = 8'd0;
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reg maccore_ethphy_liteethphygmiimiirx_mux_source_payload_last_be = 1'd0;
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reg maccore_ethphy_liteethphygmiimiirx_mux_source_payload_error = 1'd0;
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wire maccore_ethphy_liteethphygmiimiirx_mux_endpoint0_sink_valid;
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reg maccore_ethphy_liteethphygmiimiirx_mux_endpoint0_sink_ready = 1'd0;
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wire maccore_ethphy_liteethphygmiimiirx_mux_endpoint0_sink_first;
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wire maccore_ethphy_liteethphygmiimiirx_mux_endpoint0_sink_last;
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wire [7:0] maccore_ethphy_liteethphygmiimiirx_mux_endpoint0_sink_payload_data;
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wire maccore_ethphy_liteethphygmiimiirx_mux_endpoint0_sink_payload_last_be;
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wire maccore_ethphy_liteethphygmiimiirx_mux_endpoint0_sink_payload_error;
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wire maccore_ethphy_liteethphygmiimiirx_mux_endpoint1_sink_valid;
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reg maccore_ethphy_liteethphygmiimiirx_mux_endpoint1_sink_ready = 1'd0;
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wire maccore_ethphy_liteethphygmiimiirx_mux_endpoint1_sink_first;
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wire maccore_ethphy_liteethphygmiimiirx_mux_endpoint1_sink_last;
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wire [7:0] maccore_ethphy_liteethphygmiimiirx_mux_endpoint1_sink_payload_data;
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wire maccore_ethphy_liteethphygmiimiirx_mux_endpoint1_sink_payload_last_be;
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wire maccore_ethphy_liteethphygmiimiirx_mux_endpoint1_sink_payload_error;
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wire maccore_ethphy_liteethphygmiimiirx_mux_sel;
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wire maccore_ethphy_mdc;
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wire maccore_ethphy_oe;
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wire maccore_ethphy_w;
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reg [2:0] maccore_ethphy__w_storage = 3'd0;
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reg maccore_ethphy__w_re = 1'd0;
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reg maccore_ethphy_r = 1'd0;
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reg maccore_ethphy__r_status = 1'd0;
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wire maccore_ethphy__r_we;
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reg maccore_ethphy__r_re = 1'd0;
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wire maccore_ethphy_data_w;
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wire maccore_ethphy_data_oe;
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wire maccore_ethphy_data_r;
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wire tx_gap_inserter_sink_valid;
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reg tx_gap_inserter_sink_ready = 1'd0;
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wire tx_gap_inserter_sink_first;
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wire tx_gap_inserter_sink_last;
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wire [7:0] tx_gap_inserter_sink_payload_data;
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wire tx_gap_inserter_sink_payload_last_be;
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wire tx_gap_inserter_sink_payload_error;
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reg tx_gap_inserter_source_valid = 1'd0;
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wire tx_gap_inserter_source_ready;
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reg tx_gap_inserter_source_first = 1'd0;
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reg tx_gap_inserter_source_last = 1'd0;
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reg [7:0] tx_gap_inserter_source_payload_data = 8'd0;
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reg tx_gap_inserter_source_payload_last_be = 1'd0;
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reg tx_gap_inserter_source_payload_error = 1'd0;
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reg [3:0] tx_gap_inserter_counter = 4'd0;
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reg preamble_crc_status = 1'd1;
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wire preamble_crc_we;
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reg preamble_crc_re = 1'd0;
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reg [31:0] preamble_errors_status = 32'd0;
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wire preamble_errors_we;
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reg preamble_errors_re = 1'd0;
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reg [31:0] crc_errors_status = 32'd0;
|
|
wire crc_errors_we;
|
|
reg crc_errors_re = 1'd0;
|
|
wire preamble_inserter_sink_valid;
|
|
reg preamble_inserter_sink_ready = 1'd0;
|
|
wire preamble_inserter_sink_first;
|
|
wire preamble_inserter_sink_last;
|
|
wire [7:0] preamble_inserter_sink_payload_data;
|
|
wire preamble_inserter_sink_payload_last_be;
|
|
wire preamble_inserter_sink_payload_error;
|
|
reg preamble_inserter_source_valid = 1'd0;
|
|
wire preamble_inserter_source_ready;
|
|
reg preamble_inserter_source_first = 1'd0;
|
|
reg preamble_inserter_source_last = 1'd0;
|
|
reg [7:0] preamble_inserter_source_payload_data = 8'd0;
|
|
wire preamble_inserter_source_payload_last_be;
|
|
reg preamble_inserter_source_payload_error = 1'd0;
|
|
reg [63:0] preamble_inserter_preamble = 64'd15372286728091293013;
|
|
reg [2:0] preamble_inserter_count = 3'd0;
|
|
wire preamble_checker_sink_valid;
|
|
reg preamble_checker_sink_ready = 1'd0;
|
|
wire preamble_checker_sink_first;
|
|
wire preamble_checker_sink_last;
|
|
wire [7:0] preamble_checker_sink_payload_data;
|
|
wire preamble_checker_sink_payload_last_be;
|
|
wire preamble_checker_sink_payload_error;
|
|
reg preamble_checker_source_valid = 1'd0;
|
|
wire preamble_checker_source_ready;
|
|
reg preamble_checker_source_first = 1'd0;
|
|
reg preamble_checker_source_last = 1'd0;
|
|
wire [7:0] preamble_checker_source_payload_data;
|
|
wire preamble_checker_source_payload_last_be;
|
|
reg preamble_checker_source_payload_error = 1'd0;
|
|
reg preamble_checker_error = 1'd0;
|
|
wire liteethmaccrc32inserter_sink_valid;
|
|
reg liteethmaccrc32inserter_sink_ready = 1'd0;
|
|
wire liteethmaccrc32inserter_sink_first;
|
|
wire liteethmaccrc32inserter_sink_last;
|
|
wire [7:0] liteethmaccrc32inserter_sink_payload_data;
|
|
wire liteethmaccrc32inserter_sink_payload_last_be;
|
|
wire liteethmaccrc32inserter_sink_payload_error;
|
|
reg liteethmaccrc32inserter_source_valid = 1'd0;
|
|
wire liteethmaccrc32inserter_source_ready;
|
|
reg liteethmaccrc32inserter_source_first = 1'd0;
|
|
reg liteethmaccrc32inserter_source_last = 1'd0;
|
|
reg [7:0] liteethmaccrc32inserter_source_payload_data = 8'd0;
|
|
reg liteethmaccrc32inserter_source_payload_last_be = 1'd0;
|
|
reg liteethmaccrc32inserter_source_payload_error = 1'd0;
|
|
reg [7:0] liteethmaccrc32inserter_data0 = 8'd0;
|
|
wire [31:0] liteethmaccrc32inserter_value;
|
|
wire liteethmaccrc32inserter_error;
|
|
wire [7:0] liteethmaccrc32inserter_data1;
|
|
wire [31:0] liteethmaccrc32inserter_last;
|
|
reg [31:0] liteethmaccrc32inserter_next = 32'd0;
|
|
reg [31:0] liteethmaccrc32inserter_reg = 32'd4294967295;
|
|
reg liteethmaccrc32inserter_ce = 1'd0;
|
|
reg liteethmaccrc32inserter_reset = 1'd0;
|
|
reg [1:0] liteethmaccrc32inserter_cnt = 2'd3;
|
|
wire liteethmaccrc32inserter_cnt_done;
|
|
reg liteethmaccrc32inserter_is_ongoing0 = 1'd0;
|
|
reg liteethmaccrc32inserter_is_ongoing1 = 1'd0;
|
|
wire crc32_inserter_sink_valid;
|
|
wire crc32_inserter_sink_ready;
|
|
wire crc32_inserter_sink_first;
|
|
wire crc32_inserter_sink_last;
|
|
wire [7:0] crc32_inserter_sink_payload_data;
|
|
wire crc32_inserter_sink_payload_last_be;
|
|
wire crc32_inserter_sink_payload_error;
|
|
reg crc32_inserter_source_valid = 1'd0;
|
|
wire crc32_inserter_source_ready;
|
|
reg crc32_inserter_source_first = 1'd0;
|
|
reg crc32_inserter_source_last = 1'd0;
|
|
reg [7:0] crc32_inserter_source_payload_data = 8'd0;
|
|
reg crc32_inserter_source_payload_last_be = 1'd0;
|
|
reg crc32_inserter_source_payload_error = 1'd0;
|
|
wire liteethmaccrc32checker_sink_sink_valid;
|
|
reg liteethmaccrc32checker_sink_sink_ready = 1'd0;
|
|
wire liteethmaccrc32checker_sink_sink_first;
|
|
wire liteethmaccrc32checker_sink_sink_last;
|
|
wire [7:0] liteethmaccrc32checker_sink_sink_payload_data;
|
|
wire liteethmaccrc32checker_sink_sink_payload_last_be;
|
|
wire liteethmaccrc32checker_sink_sink_payload_error;
|
|
wire liteethmaccrc32checker_source_source_valid;
|
|
wire liteethmaccrc32checker_source_source_ready;
|
|
reg liteethmaccrc32checker_source_source_first = 1'd0;
|
|
wire liteethmaccrc32checker_source_source_last;
|
|
wire [7:0] liteethmaccrc32checker_source_source_payload_data;
|
|
wire liteethmaccrc32checker_source_source_payload_last_be;
|
|
reg liteethmaccrc32checker_source_source_payload_error = 1'd0;
|
|
wire liteethmaccrc32checker_error;
|
|
wire [7:0] liteethmaccrc32checker_crc_data0;
|
|
wire [31:0] liteethmaccrc32checker_crc_value;
|
|
wire liteethmaccrc32checker_crc_error;
|
|
wire [7:0] liteethmaccrc32checker_crc_data1;
|
|
wire [31:0] liteethmaccrc32checker_crc_last;
|
|
reg [31:0] liteethmaccrc32checker_crc_next = 32'd0;
|
|
reg [31:0] liteethmaccrc32checker_crc_reg = 32'd4294967295;
|
|
reg liteethmaccrc32checker_crc_ce = 1'd0;
|
|
reg liteethmaccrc32checker_crc_reset = 1'd0;
|
|
reg liteethmaccrc32checker_syncfifo_sink_valid = 1'd0;
|
|
wire liteethmaccrc32checker_syncfifo_sink_ready;
|
|
wire liteethmaccrc32checker_syncfifo_sink_first;
|
|
wire liteethmaccrc32checker_syncfifo_sink_last;
|
|
wire [7:0] liteethmaccrc32checker_syncfifo_sink_payload_data;
|
|
wire liteethmaccrc32checker_syncfifo_sink_payload_last_be;
|
|
wire liteethmaccrc32checker_syncfifo_sink_payload_error;
|
|
wire liteethmaccrc32checker_syncfifo_source_valid;
|
|
wire liteethmaccrc32checker_syncfifo_source_ready;
|
|
wire liteethmaccrc32checker_syncfifo_source_first;
|
|
wire liteethmaccrc32checker_syncfifo_source_last;
|
|
wire [7:0] liteethmaccrc32checker_syncfifo_source_payload_data;
|
|
wire liteethmaccrc32checker_syncfifo_source_payload_last_be;
|
|
wire liteethmaccrc32checker_syncfifo_source_payload_error;
|
|
wire liteethmaccrc32checker_syncfifo_syncfifo_we;
|
|
wire liteethmaccrc32checker_syncfifo_syncfifo_writable;
|
|
wire liteethmaccrc32checker_syncfifo_syncfifo_re;
|
|
wire liteethmaccrc32checker_syncfifo_syncfifo_readable;
|
|
wire [11:0] liteethmaccrc32checker_syncfifo_syncfifo_din;
|
|
wire [11:0] liteethmaccrc32checker_syncfifo_syncfifo_dout;
|
|
reg [2:0] liteethmaccrc32checker_syncfifo_level = 3'd0;
|
|
reg liteethmaccrc32checker_syncfifo_replace = 1'd0;
|
|
reg [2:0] liteethmaccrc32checker_syncfifo_produce = 3'd0;
|
|
reg [2:0] liteethmaccrc32checker_syncfifo_consume = 3'd0;
|
|
reg [2:0] liteethmaccrc32checker_syncfifo_wrport_adr = 3'd0;
|
|
wire [11:0] liteethmaccrc32checker_syncfifo_wrport_dat_r;
|
|
wire liteethmaccrc32checker_syncfifo_wrport_we;
|
|
wire [11:0] liteethmaccrc32checker_syncfifo_wrport_dat_w;
|
|
wire liteethmaccrc32checker_syncfifo_do_read;
|
|
wire [2:0] liteethmaccrc32checker_syncfifo_rdport_adr;
|
|
wire [11:0] liteethmaccrc32checker_syncfifo_rdport_dat_r;
|
|
wire [7:0] liteethmaccrc32checker_syncfifo_fifo_in_payload_data;
|
|
wire liteethmaccrc32checker_syncfifo_fifo_in_payload_last_be;
|
|
wire liteethmaccrc32checker_syncfifo_fifo_in_payload_error;
|
|
wire liteethmaccrc32checker_syncfifo_fifo_in_first;
|
|
wire liteethmaccrc32checker_syncfifo_fifo_in_last;
|
|
wire [7:0] liteethmaccrc32checker_syncfifo_fifo_out_payload_data;
|
|
wire liteethmaccrc32checker_syncfifo_fifo_out_payload_last_be;
|
|
wire liteethmaccrc32checker_syncfifo_fifo_out_payload_error;
|
|
wire liteethmaccrc32checker_syncfifo_fifo_out_first;
|
|
wire liteethmaccrc32checker_syncfifo_fifo_out_last;
|
|
reg liteethmaccrc32checker_fifo_reset = 1'd0;
|
|
wire liteethmaccrc32checker_fifo_in;
|
|
wire liteethmaccrc32checker_fifo_out;
|
|
wire liteethmaccrc32checker_fifo_full;
|
|
wire crc32_checker_sink_valid;
|
|
wire crc32_checker_sink_ready;
|
|
wire crc32_checker_sink_first;
|
|
wire crc32_checker_sink_last;
|
|
wire [7:0] crc32_checker_sink_payload_data;
|
|
wire crc32_checker_sink_payload_last_be;
|
|
wire crc32_checker_sink_payload_error;
|
|
reg crc32_checker_source_valid = 1'd0;
|
|
wire crc32_checker_source_ready;
|
|
reg crc32_checker_source_first = 1'd0;
|
|
reg crc32_checker_source_last = 1'd0;
|
|
reg [7:0] crc32_checker_source_payload_data = 8'd0;
|
|
reg crc32_checker_source_payload_last_be = 1'd0;
|
|
reg crc32_checker_source_payload_error = 1'd0;
|
|
wire ps_preamble_error_i;
|
|
wire ps_preamble_error_o;
|
|
reg ps_preamble_error_toggle_i = 1'd0;
|
|
wire ps_preamble_error_toggle_o;
|
|
reg ps_preamble_error_toggle_o_r = 1'd0;
|
|
wire ps_crc_error_i;
|
|
wire ps_crc_error_o;
|
|
reg ps_crc_error_toggle_i = 1'd0;
|
|
wire ps_crc_error_toggle_o;
|
|
reg ps_crc_error_toggle_o_r = 1'd0;
|
|
wire padding_inserter_sink_valid;
|
|
reg padding_inserter_sink_ready = 1'd0;
|
|
wire padding_inserter_sink_first;
|
|
wire padding_inserter_sink_last;
|
|
wire [7:0] padding_inserter_sink_payload_data;
|
|
wire padding_inserter_sink_payload_last_be;
|
|
wire padding_inserter_sink_payload_error;
|
|
reg padding_inserter_source_valid = 1'd0;
|
|
wire padding_inserter_source_ready;
|
|
reg padding_inserter_source_first = 1'd0;
|
|
reg padding_inserter_source_last = 1'd0;
|
|
reg [7:0] padding_inserter_source_payload_data = 8'd0;
|
|
reg padding_inserter_source_payload_last_be = 1'd0;
|
|
reg padding_inserter_source_payload_error = 1'd0;
|
|
reg [15:0] padding_inserter_counter = 16'd0;
|
|
wire padding_inserter_counter_done;
|
|
wire padding_checker_sink_valid;
|
|
wire padding_checker_sink_ready;
|
|
wire padding_checker_sink_first;
|
|
wire padding_checker_sink_last;
|
|
wire [7:0] padding_checker_sink_payload_data;
|
|
wire padding_checker_sink_payload_last_be;
|
|
wire padding_checker_sink_payload_error;
|
|
wire padding_checker_source_valid;
|
|
wire padding_checker_source_ready;
|
|
wire padding_checker_source_first;
|
|
wire padding_checker_source_last;
|
|
wire [7:0] padding_checker_source_payload_data;
|
|
wire padding_checker_source_payload_last_be;
|
|
wire padding_checker_source_payload_error;
|
|
wire tx_last_be_sink_valid;
|
|
reg tx_last_be_sink_ready = 1'd0;
|
|
wire tx_last_be_sink_first;
|
|
wire tx_last_be_sink_last;
|
|
wire [7:0] tx_last_be_sink_payload_data;
|
|
wire tx_last_be_sink_payload_last_be;
|
|
wire tx_last_be_sink_payload_error;
|
|
reg tx_last_be_source_valid = 1'd0;
|
|
wire tx_last_be_source_ready;
|
|
reg tx_last_be_source_first = 1'd0;
|
|
reg tx_last_be_source_last = 1'd0;
|
|
reg [7:0] tx_last_be_source_payload_data = 8'd0;
|
|
reg tx_last_be_source_payload_last_be = 1'd0;
|
|
reg tx_last_be_source_payload_error = 1'd0;
|
|
wire rx_last_be_sink_valid;
|
|
wire rx_last_be_sink_ready;
|
|
wire rx_last_be_sink_first;
|
|
wire rx_last_be_sink_last;
|
|
wire [7:0] rx_last_be_sink_payload_data;
|
|
wire rx_last_be_sink_payload_last_be;
|
|
wire rx_last_be_sink_payload_error;
|
|
wire rx_last_be_source_valid;
|
|
wire rx_last_be_source_ready;
|
|
wire rx_last_be_source_first;
|
|
wire rx_last_be_source_last;
|
|
wire [7:0] rx_last_be_source_payload_data;
|
|
reg rx_last_be_source_payload_last_be = 1'd0;
|
|
wire rx_last_be_source_payload_error;
|
|
wire tx_converter_sink_valid;
|
|
wire tx_converter_sink_ready;
|
|
wire tx_converter_sink_first;
|
|
wire tx_converter_sink_last;
|
|
wire [31:0] tx_converter_sink_payload_data;
|
|
wire [3:0] tx_converter_sink_payload_last_be;
|
|
wire [3:0] tx_converter_sink_payload_error;
|
|
wire tx_converter_source_valid;
|
|
wire tx_converter_source_ready;
|
|
wire tx_converter_source_first;
|
|
wire tx_converter_source_last;
|
|
wire [7:0] tx_converter_source_payload_data;
|
|
wire tx_converter_source_payload_last_be;
|
|
wire tx_converter_source_payload_error;
|
|
wire tx_converter_converter_sink_valid;
|
|
wire tx_converter_converter_sink_ready;
|
|
wire tx_converter_converter_sink_first;
|
|
wire tx_converter_converter_sink_last;
|
|
reg [39:0] tx_converter_converter_sink_payload_data = 40'd0;
|
|
wire tx_converter_converter_source_valid;
|
|
wire tx_converter_converter_source_ready;
|
|
wire tx_converter_converter_source_first;
|
|
wire tx_converter_converter_source_last;
|
|
reg [9:0] tx_converter_converter_source_payload_data = 10'd0;
|
|
wire tx_converter_converter_source_payload_valid_token_count;
|
|
reg [1:0] tx_converter_converter_mux = 2'd0;
|
|
wire tx_converter_converter_first;
|
|
wire tx_converter_converter_last;
|
|
wire tx_converter_source_source_valid;
|
|
wire tx_converter_source_source_ready;
|
|
wire tx_converter_source_source_first;
|
|
wire tx_converter_source_source_last;
|
|
wire [9:0] tx_converter_source_source_payload_data;
|
|
wire rx_converter_sink_valid;
|
|
wire rx_converter_sink_ready;
|
|
wire rx_converter_sink_first;
|
|
wire rx_converter_sink_last;
|
|
wire [7:0] rx_converter_sink_payload_data;
|
|
wire rx_converter_sink_payload_last_be;
|
|
wire rx_converter_sink_payload_error;
|
|
wire rx_converter_source_valid;
|
|
wire rx_converter_source_ready;
|
|
wire rx_converter_source_first;
|
|
wire rx_converter_source_last;
|
|
reg [31:0] rx_converter_source_payload_data = 32'd0;
|
|
reg [3:0] rx_converter_source_payload_last_be = 4'd0;
|
|
reg [3:0] rx_converter_source_payload_error = 4'd0;
|
|
wire rx_converter_converter_sink_valid;
|
|
wire rx_converter_converter_sink_ready;
|
|
wire rx_converter_converter_sink_first;
|
|
wire rx_converter_converter_sink_last;
|
|
wire [9:0] rx_converter_converter_sink_payload_data;
|
|
wire rx_converter_converter_source_valid;
|
|
wire rx_converter_converter_source_ready;
|
|
reg rx_converter_converter_source_first = 1'd0;
|
|
reg rx_converter_converter_source_last = 1'd0;
|
|
reg [39:0] rx_converter_converter_source_payload_data = 40'd0;
|
|
reg [2:0] rx_converter_converter_source_payload_valid_token_count = 3'd0;
|
|
reg [1:0] rx_converter_converter_demux = 2'd0;
|
|
wire rx_converter_converter_load_part;
|
|
reg rx_converter_converter_strobe_all = 1'd0;
|
|
wire rx_converter_source_source_valid;
|
|
wire rx_converter_source_source_ready;
|
|
wire rx_converter_source_source_first;
|
|
wire rx_converter_source_source_last;
|
|
wire [39:0] rx_converter_source_source_payload_data;
|
|
wire tx_cdc_sink_sink_valid;
|
|
wire tx_cdc_sink_sink_ready;
|
|
wire tx_cdc_sink_sink_first;
|
|
wire tx_cdc_sink_sink_last;
|
|
wire [31:0] tx_cdc_sink_sink_payload_data;
|
|
wire [3:0] tx_cdc_sink_sink_payload_last_be;
|
|
wire [3:0] tx_cdc_sink_sink_payload_error;
|
|
wire tx_cdc_source_source_valid;
|
|
wire tx_cdc_source_source_ready;
|
|
wire tx_cdc_source_source_first;
|
|
wire tx_cdc_source_source_last;
|
|
wire [31:0] tx_cdc_source_source_payload_data;
|
|
wire [3:0] tx_cdc_source_source_payload_last_be;
|
|
wire [3:0] tx_cdc_source_source_payload_error;
|
|
wire tx_cdc_cdc_sink_valid;
|
|
wire tx_cdc_cdc_sink_ready;
|
|
wire tx_cdc_cdc_sink_first;
|
|
wire tx_cdc_cdc_sink_last;
|
|
wire [31:0] tx_cdc_cdc_sink_payload_data;
|
|
wire [3:0] tx_cdc_cdc_sink_payload_last_be;
|
|
wire [3:0] tx_cdc_cdc_sink_payload_error;
|
|
wire tx_cdc_cdc_source_valid;
|
|
wire tx_cdc_cdc_source_ready;
|
|
wire tx_cdc_cdc_source_first;
|
|
wire tx_cdc_cdc_source_last;
|
|
wire [31:0] tx_cdc_cdc_source_payload_data;
|
|
wire [3:0] tx_cdc_cdc_source_payload_last_be;
|
|
wire [3:0] tx_cdc_cdc_source_payload_error;
|
|
wire tx_cdc_cdc_asyncfifo_we;
|
|
wire tx_cdc_cdc_asyncfifo_writable;
|
|
wire tx_cdc_cdc_asyncfifo_re;
|
|
wire tx_cdc_cdc_asyncfifo_readable;
|
|
wire [41:0] tx_cdc_cdc_asyncfifo_din;
|
|
wire [41:0] tx_cdc_cdc_asyncfifo_dout;
|
|
wire tx_cdc_cdc_graycounter0_ce;
|
|
(* dont_touch = "true" *) reg [5:0] tx_cdc_cdc_graycounter0_q = 6'd0;
|
|
wire [5:0] tx_cdc_cdc_graycounter0_q_next;
|
|
reg [5:0] tx_cdc_cdc_graycounter0_q_binary = 6'd0;
|
|
reg [5:0] tx_cdc_cdc_graycounter0_q_next_binary = 6'd0;
|
|
wire tx_cdc_cdc_graycounter1_ce;
|
|
(* dont_touch = "true" *) reg [5:0] tx_cdc_cdc_graycounter1_q = 6'd0;
|
|
wire [5:0] tx_cdc_cdc_graycounter1_q_next;
|
|
reg [5:0] tx_cdc_cdc_graycounter1_q_binary = 6'd0;
|
|
reg [5:0] tx_cdc_cdc_graycounter1_q_next_binary = 6'd0;
|
|
wire [5:0] tx_cdc_cdc_produce_rdomain;
|
|
wire [5:0] tx_cdc_cdc_consume_wdomain;
|
|
wire [4:0] tx_cdc_cdc_wrport_adr;
|
|
wire [41:0] tx_cdc_cdc_wrport_dat_r;
|
|
wire tx_cdc_cdc_wrport_we;
|
|
wire [41:0] tx_cdc_cdc_wrport_dat_w;
|
|
wire [4:0] tx_cdc_cdc_rdport_adr;
|
|
wire [41:0] tx_cdc_cdc_rdport_dat_r;
|
|
wire [31:0] tx_cdc_cdc_fifo_in_payload_data;
|
|
wire [3:0] tx_cdc_cdc_fifo_in_payload_last_be;
|
|
wire [3:0] tx_cdc_cdc_fifo_in_payload_error;
|
|
wire tx_cdc_cdc_fifo_in_first;
|
|
wire tx_cdc_cdc_fifo_in_last;
|
|
wire [31:0] tx_cdc_cdc_fifo_out_payload_data;
|
|
wire [3:0] tx_cdc_cdc_fifo_out_payload_last_be;
|
|
wire [3:0] tx_cdc_cdc_fifo_out_payload_error;
|
|
wire tx_cdc_cdc_fifo_out_first;
|
|
wire tx_cdc_cdc_fifo_out_last;
|
|
wire rx_cdc_sink_sink_valid;
|
|
wire rx_cdc_sink_sink_ready;
|
|
wire rx_cdc_sink_sink_first;
|
|
wire rx_cdc_sink_sink_last;
|
|
wire [31:0] rx_cdc_sink_sink_payload_data;
|
|
wire [3:0] rx_cdc_sink_sink_payload_last_be;
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|
wire [3:0] rx_cdc_sink_sink_payload_error;
|
|
wire rx_cdc_source_source_valid;
|
|
wire rx_cdc_source_source_ready;
|
|
wire rx_cdc_source_source_first;
|
|
wire rx_cdc_source_source_last;
|
|
wire [31:0] rx_cdc_source_source_payload_data;
|
|
wire [3:0] rx_cdc_source_source_payload_last_be;
|
|
wire [3:0] rx_cdc_source_source_payload_error;
|
|
wire rx_cdc_cdc_sink_valid;
|
|
wire rx_cdc_cdc_sink_ready;
|
|
wire rx_cdc_cdc_sink_first;
|
|
wire rx_cdc_cdc_sink_last;
|
|
wire [31:0] rx_cdc_cdc_sink_payload_data;
|
|
wire [3:0] rx_cdc_cdc_sink_payload_last_be;
|
|
wire [3:0] rx_cdc_cdc_sink_payload_error;
|
|
wire rx_cdc_cdc_source_valid;
|
|
wire rx_cdc_cdc_source_ready;
|
|
wire rx_cdc_cdc_source_first;
|
|
wire rx_cdc_cdc_source_last;
|
|
wire [31:0] rx_cdc_cdc_source_payload_data;
|
|
wire [3:0] rx_cdc_cdc_source_payload_last_be;
|
|
wire [3:0] rx_cdc_cdc_source_payload_error;
|
|
wire rx_cdc_cdc_asyncfifo_we;
|
|
wire rx_cdc_cdc_asyncfifo_writable;
|
|
wire rx_cdc_cdc_asyncfifo_re;
|
|
wire rx_cdc_cdc_asyncfifo_readable;
|
|
wire [41:0] rx_cdc_cdc_asyncfifo_din;
|
|
wire [41:0] rx_cdc_cdc_asyncfifo_dout;
|
|
wire rx_cdc_cdc_graycounter0_ce;
|
|
(* dont_touch = "true" *) reg [5:0] rx_cdc_cdc_graycounter0_q = 6'd0;
|
|
wire [5:0] rx_cdc_cdc_graycounter0_q_next;
|
|
reg [5:0] rx_cdc_cdc_graycounter0_q_binary = 6'd0;
|
|
reg [5:0] rx_cdc_cdc_graycounter0_q_next_binary = 6'd0;
|
|
wire rx_cdc_cdc_graycounter1_ce;
|
|
(* dont_touch = "true" *) reg [5:0] rx_cdc_cdc_graycounter1_q = 6'd0;
|
|
wire [5:0] rx_cdc_cdc_graycounter1_q_next;
|
|
reg [5:0] rx_cdc_cdc_graycounter1_q_binary = 6'd0;
|
|
reg [5:0] rx_cdc_cdc_graycounter1_q_next_binary = 6'd0;
|
|
wire [5:0] rx_cdc_cdc_produce_rdomain;
|
|
wire [5:0] rx_cdc_cdc_consume_wdomain;
|
|
wire [4:0] rx_cdc_cdc_wrport_adr;
|
|
wire [41:0] rx_cdc_cdc_wrport_dat_r;
|
|
wire rx_cdc_cdc_wrport_we;
|
|
wire [41:0] rx_cdc_cdc_wrport_dat_w;
|
|
wire [4:0] rx_cdc_cdc_rdport_adr;
|
|
wire [41:0] rx_cdc_cdc_rdport_dat_r;
|
|
wire [31:0] rx_cdc_cdc_fifo_in_payload_data;
|
|
wire [3:0] rx_cdc_cdc_fifo_in_payload_last_be;
|
|
wire [3:0] rx_cdc_cdc_fifo_in_payload_error;
|
|
wire rx_cdc_cdc_fifo_in_first;
|
|
wire rx_cdc_cdc_fifo_in_last;
|
|
wire [31:0] rx_cdc_cdc_fifo_out_payload_data;
|
|
wire [3:0] rx_cdc_cdc_fifo_out_payload_last_be;
|
|
wire [3:0] rx_cdc_cdc_fifo_out_payload_error;
|
|
wire rx_cdc_cdc_fifo_out_first;
|
|
wire rx_cdc_cdc_fifo_out_last;
|
|
wire sink_valid;
|
|
wire sink_ready;
|
|
wire sink_first;
|
|
wire sink_last;
|
|
wire [31:0] sink_payload_data;
|
|
wire [3:0] sink_payload_last_be;
|
|
wire [3:0] sink_payload_error;
|
|
wire source_valid;
|
|
wire source_ready;
|
|
wire source_first;
|
|
wire source_last;
|
|
wire [31:0] source_payload_data;
|
|
wire [3:0] source_payload_last_be;
|
|
wire [3:0] source_payload_error;
|
|
wire [29:0] bus_adr;
|
|
wire [31:0] bus_dat_w;
|
|
wire [31:0] bus_dat_r;
|
|
wire [3:0] bus_sel;
|
|
wire bus_cyc;
|
|
wire bus_stb;
|
|
wire bus_ack;
|
|
wire bus_we;
|
|
wire [2:0] bus_cti;
|
|
wire [1:0] bus_bte;
|
|
wire bus_err;
|
|
wire writer_sink_sink_valid;
|
|
reg writer_sink_sink_ready = 1'd1;
|
|
wire writer_sink_sink_first;
|
|
wire writer_sink_sink_last;
|
|
wire [31:0] writer_sink_sink_payload_data;
|
|
wire [3:0] writer_sink_sink_payload_last_be;
|
|
wire [3:0] writer_sink_sink_payload_error;
|
|
wire writer_slot_status;
|
|
wire writer_slot_we;
|
|
reg writer_slot_re = 1'd0;
|
|
wire [31:0] writer_length_status;
|
|
wire writer_length_we;
|
|
reg writer_length_re = 1'd0;
|
|
reg [31:0] writer_errors_status = 32'd0;
|
|
wire writer_errors_we;
|
|
reg writer_errors_re = 1'd0;
|
|
wire writer_irq;
|
|
wire writer_available_status;
|
|
wire writer_available_pending;
|
|
wire writer_available_trigger;
|
|
reg writer_available_clear = 1'd0;
|
|
wire writer_available0;
|
|
wire writer_status_status;
|
|
wire writer_status_we;
|
|
reg writer_status_re = 1'd0;
|
|
wire writer_available1;
|
|
wire writer_pending_status;
|
|
wire writer_pending_we;
|
|
reg writer_pending_re = 1'd0;
|
|
reg writer_pending_r = 1'd0;
|
|
wire writer_available2;
|
|
reg writer_enable_storage = 1'd0;
|
|
reg writer_enable_re = 1'd0;
|
|
reg [2:0] writer_inc = 3'd0;
|
|
reg [31:0] writer_counter = 32'd0;
|
|
reg writer_slot = 1'd0;
|
|
reg writer_slot_ce = 1'd0;
|
|
reg writer_start = 1'd0;
|
|
reg writer_ongoing = 1'd0;
|
|
reg writer_stat_fifo_sink_valid = 1'd0;
|
|
wire writer_stat_fifo_sink_ready;
|
|
reg writer_stat_fifo_sink_first = 1'd0;
|
|
reg writer_stat_fifo_sink_last = 1'd0;
|
|
wire writer_stat_fifo_sink_payload_slot;
|
|
wire [31:0] writer_stat_fifo_sink_payload_length;
|
|
wire writer_stat_fifo_source_valid;
|
|
wire writer_stat_fifo_source_ready;
|
|
wire writer_stat_fifo_source_first;
|
|
wire writer_stat_fifo_source_last;
|
|
wire writer_stat_fifo_source_payload_slot;
|
|
wire [31:0] writer_stat_fifo_source_payload_length;
|
|
wire writer_stat_fifo_syncfifo_we;
|
|
wire writer_stat_fifo_syncfifo_writable;
|
|
wire writer_stat_fifo_syncfifo_re;
|
|
wire writer_stat_fifo_syncfifo_readable;
|
|
wire [34:0] writer_stat_fifo_syncfifo_din;
|
|
wire [34:0] writer_stat_fifo_syncfifo_dout;
|
|
reg [1:0] writer_stat_fifo_level = 2'd0;
|
|
reg writer_stat_fifo_replace = 1'd0;
|
|
reg writer_stat_fifo_produce = 1'd0;
|
|
reg writer_stat_fifo_consume = 1'd0;
|
|
reg writer_stat_fifo_wrport_adr = 1'd0;
|
|
wire [34:0] writer_stat_fifo_wrport_dat_r;
|
|
wire writer_stat_fifo_wrport_we;
|
|
wire [34:0] writer_stat_fifo_wrport_dat_w;
|
|
wire writer_stat_fifo_do_read;
|
|
wire writer_stat_fifo_rdport_adr;
|
|
wire [34:0] writer_stat_fifo_rdport_dat_r;
|
|
wire writer_stat_fifo_fifo_in_payload_slot;
|
|
wire [31:0] writer_stat_fifo_fifo_in_payload_length;
|
|
wire writer_stat_fifo_fifo_in_first;
|
|
wire writer_stat_fifo_fifo_in_last;
|
|
wire writer_stat_fifo_fifo_out_payload_slot;
|
|
wire [31:0] writer_stat_fifo_fifo_out_payload_length;
|
|
wire writer_stat_fifo_fifo_out_first;
|
|
wire writer_stat_fifo_fifo_out_last;
|
|
reg [8:0] writer_memory0_adr = 9'd0;
|
|
wire [31:0] writer_memory0_dat_r;
|
|
reg writer_memory0_we = 1'd0;
|
|
reg [31:0] writer_memory0_dat_w = 32'd0;
|
|
reg [8:0] writer_memory1_adr = 9'd0;
|
|
wire [31:0] writer_memory1_dat_r;
|
|
reg writer_memory1_we = 1'd0;
|
|
reg [31:0] writer_memory1_dat_w = 32'd0;
|
|
reg reader_source_source_valid = 1'd0;
|
|
wire reader_source_source_ready;
|
|
reg reader_source_source_first = 1'd0;
|
|
reg reader_source_source_last = 1'd0;
|
|
reg [31:0] reader_source_source_payload_data = 32'd0;
|
|
reg [3:0] reader_source_source_payload_last_be = 4'd0;
|
|
reg [3:0] reader_source_source_payload_error = 4'd0;
|
|
reg reader_start_start_re = 1'd0;
|
|
wire reader_start_start_r;
|
|
reg reader_start_start_we = 1'd0;
|
|
reg reader_start_start_w = 1'd0;
|
|
wire reader_ready_status;
|
|
wire reader_ready_we;
|
|
reg reader_ready_re = 1'd0;
|
|
wire [1:0] reader_level_status;
|
|
wire reader_level_we;
|
|
reg reader_level_re = 1'd0;
|
|
reg reader_slot_storage = 1'd0;
|
|
reg reader_slot_re = 1'd0;
|
|
reg [10:0] reader_length_storage = 11'd0;
|
|
reg reader_length_re = 1'd0;
|
|
wire reader_irq;
|
|
wire reader_eventsourcepulse_status;
|
|
reg reader_eventsourcepulse_pending = 1'd0;
|
|
reg reader_eventsourcepulse_trigger = 1'd0;
|
|
reg reader_eventsourcepulse_clear = 1'd0;
|
|
wire reader_event00;
|
|
wire reader_status_status;
|
|
wire reader_status_we;
|
|
reg reader_status_re = 1'd0;
|
|
wire reader_event01;
|
|
wire reader_pending_status;
|
|
wire reader_pending_we;
|
|
reg reader_pending_re = 1'd0;
|
|
reg reader_pending_r = 1'd0;
|
|
wire reader_event02;
|
|
reg reader_enable_storage = 1'd0;
|
|
reg reader_enable_re = 1'd0;
|
|
reg reader_start = 1'd0;
|
|
wire reader_cmd_fifo_sink_valid;
|
|
wire reader_cmd_fifo_sink_ready;
|
|
reg reader_cmd_fifo_sink_first = 1'd0;
|
|
reg reader_cmd_fifo_sink_last = 1'd0;
|
|
wire reader_cmd_fifo_sink_payload_slot;
|
|
wire [10:0] reader_cmd_fifo_sink_payload_length;
|
|
wire reader_cmd_fifo_source_valid;
|
|
reg reader_cmd_fifo_source_ready = 1'd0;
|
|
wire reader_cmd_fifo_source_first;
|
|
wire reader_cmd_fifo_source_last;
|
|
wire reader_cmd_fifo_source_payload_slot;
|
|
wire [10:0] reader_cmd_fifo_source_payload_length;
|
|
wire reader_cmd_fifo_syncfifo_we;
|
|
wire reader_cmd_fifo_syncfifo_writable;
|
|
wire reader_cmd_fifo_syncfifo_re;
|
|
wire reader_cmd_fifo_syncfifo_readable;
|
|
wire [13:0] reader_cmd_fifo_syncfifo_din;
|
|
wire [13:0] reader_cmd_fifo_syncfifo_dout;
|
|
reg [1:0] reader_cmd_fifo_level = 2'd0;
|
|
reg reader_cmd_fifo_replace = 1'd0;
|
|
reg reader_cmd_fifo_produce = 1'd0;
|
|
reg reader_cmd_fifo_consume = 1'd0;
|
|
reg reader_cmd_fifo_wrport_adr = 1'd0;
|
|
wire [13:0] reader_cmd_fifo_wrport_dat_r;
|
|
wire reader_cmd_fifo_wrport_we;
|
|
wire [13:0] reader_cmd_fifo_wrport_dat_w;
|
|
wire reader_cmd_fifo_do_read;
|
|
wire reader_cmd_fifo_rdport_adr;
|
|
wire [13:0] reader_cmd_fifo_rdport_dat_r;
|
|
wire reader_cmd_fifo_fifo_in_payload_slot;
|
|
wire [10:0] reader_cmd_fifo_fifo_in_payload_length;
|
|
wire reader_cmd_fifo_fifo_in_first;
|
|
wire reader_cmd_fifo_fifo_in_last;
|
|
wire reader_cmd_fifo_fifo_out_payload_slot;
|
|
wire [10:0] reader_cmd_fifo_fifo_out_payload_length;
|
|
wire reader_cmd_fifo_fifo_out_first;
|
|
wire reader_cmd_fifo_fifo_out_last;
|
|
reg [10:0] reader_read_address = 11'd0;
|
|
reg [10:0] reader_counter = 11'd0;
|
|
wire [8:0] reader_memory0_adr;
|
|
wire [31:0] reader_memory0_dat_r;
|
|
wire [8:0] reader_memory1_adr;
|
|
wire [31:0] reader_memory1_dat_r;
|
|
wire ev_irq;
|
|
wire [29:0] sram0_bus_adr0;
|
|
wire [31:0] sram0_bus_dat_w0;
|
|
wire [31:0] sram0_bus_dat_r0;
|
|
wire [3:0] sram0_bus_sel0;
|
|
wire sram0_bus_cyc0;
|
|
wire sram0_bus_stb0;
|
|
reg sram0_bus_ack0 = 1'd0;
|
|
wire sram0_bus_we0;
|
|
wire [2:0] sram0_bus_cti0;
|
|
wire [1:0] sram0_bus_bte0;
|
|
reg sram0_bus_err0 = 1'd0;
|
|
wire [8:0] sram0_adr0;
|
|
wire [31:0] sram0_dat_r0;
|
|
wire [29:0] sram1_bus_adr0;
|
|
wire [31:0] sram1_bus_dat_w0;
|
|
wire [31:0] sram1_bus_dat_r0;
|
|
wire [3:0] sram1_bus_sel0;
|
|
wire sram1_bus_cyc0;
|
|
wire sram1_bus_stb0;
|
|
reg sram1_bus_ack0 = 1'd0;
|
|
wire sram1_bus_we0;
|
|
wire [2:0] sram1_bus_cti0;
|
|
wire [1:0] sram1_bus_bte0;
|
|
reg sram1_bus_err0 = 1'd0;
|
|
wire [8:0] sram1_adr0;
|
|
wire [31:0] sram1_dat_r0;
|
|
wire [29:0] sram0_bus_adr1;
|
|
wire [31:0] sram0_bus_dat_w1;
|
|
wire [31:0] sram0_bus_dat_r1;
|
|
wire [3:0] sram0_bus_sel1;
|
|
wire sram0_bus_cyc1;
|
|
wire sram0_bus_stb1;
|
|
reg sram0_bus_ack1 = 1'd0;
|
|
wire sram0_bus_we1;
|
|
wire [2:0] sram0_bus_cti1;
|
|
wire [1:0] sram0_bus_bte1;
|
|
reg sram0_bus_err1 = 1'd0;
|
|
wire [8:0] sram0_adr1;
|
|
wire [31:0] sram0_dat_r1;
|
|
reg [3:0] sram0_we = 4'd0;
|
|
wire [31:0] sram0_dat_w;
|
|
wire [29:0] sram1_bus_adr1;
|
|
wire [31:0] sram1_bus_dat_w1;
|
|
wire [31:0] sram1_bus_dat_r1;
|
|
wire [3:0] sram1_bus_sel1;
|
|
wire sram1_bus_cyc1;
|
|
wire sram1_bus_stb1;
|
|
reg sram1_bus_ack1 = 1'd0;
|
|
wire sram1_bus_we1;
|
|
wire [2:0] sram1_bus_cti1;
|
|
wire [1:0] sram1_bus_bte1;
|
|
reg sram1_bus_err1 = 1'd0;
|
|
wire [8:0] sram1_adr1;
|
|
wire [31:0] sram1_dat_r1;
|
|
reg [3:0] sram1_we = 4'd0;
|
|
wire [31:0] sram1_dat_w;
|
|
reg [3:0] slave_sel = 4'd0;
|
|
reg [3:0] slave_sel_r = 4'd0;
|
|
wire [29:0] wb_bus_adr;
|
|
wire [31:0] wb_bus_dat_w;
|
|
wire [31:0] wb_bus_dat_r;
|
|
wire [3:0] wb_bus_sel;
|
|
wire wb_bus_cyc;
|
|
wire wb_bus_stb;
|
|
wire wb_bus_ack;
|
|
wire wb_bus_we;
|
|
wire [2:0] wb_bus_cti;
|
|
wire [1:0] wb_bus_bte;
|
|
wire wb_bus_err;
|
|
reg [1:0] subfragments_state = 2'd0;
|
|
reg [1:0] subfragments_next_state = 2'd0;
|
|
reg subfragments_liteethmacgap_state = 1'd0;
|
|
reg subfragments_liteethmacgap_next_state = 1'd0;
|
|
reg [3:0] tx_gap_inserter_counter_liteethmacgap_next_value = 4'd0;
|
|
reg tx_gap_inserter_counter_liteethmacgap_next_value_ce = 1'd0;
|
|
reg [1:0] subfragments_liteethmacpreambleinserter_state = 2'd0;
|
|
reg [1:0] subfragments_liteethmacpreambleinserter_next_state = 2'd0;
|
|
reg [2:0] preamble_inserter_count_liteethmacpreambleinserter_next_value = 3'd0;
|
|
reg preamble_inserter_count_liteethmacpreambleinserter_next_value_ce = 1'd0;
|
|
reg subfragments_liteethmacpreamblechecker_state = 1'd0;
|
|
reg subfragments_liteethmacpreamblechecker_next_state = 1'd0;
|
|
reg [1:0] subfragments_liteethmaccrc32inserter_state = 2'd0;
|
|
reg [1:0] subfragments_liteethmaccrc32inserter_next_state = 2'd0;
|
|
reg [1:0] subfragments_liteethmaccrc32checker_state = 2'd0;
|
|
reg [1:0] subfragments_liteethmaccrc32checker_next_state = 2'd0;
|
|
reg subfragments_liteethmacpaddinginserter_state = 1'd0;
|
|
reg subfragments_liteethmacpaddinginserter_next_state = 1'd0;
|
|
reg [15:0] padding_inserter_counter_liteethmacpaddinginserter_next_value = 16'd0;
|
|
reg padding_inserter_counter_liteethmacpaddinginserter_next_value_ce = 1'd0;
|
|
reg subfragments_liteethmactxlastbe_state = 1'd0;
|
|
reg subfragments_liteethmactxlastbe_next_state = 1'd0;
|
|
reg [2:0] subfragments_liteethmacsramwriter_state = 3'd0;
|
|
reg [2:0] subfragments_liteethmacsramwriter_next_state = 3'd0;
|
|
reg [31:0] writer_counter_t_next_value = 32'd0;
|
|
reg writer_counter_t_next_value_ce = 1'd0;
|
|
reg [31:0] writer_errors_status_f_next_value = 32'd0;
|
|
reg writer_errors_status_f_next_value_ce = 1'd0;
|
|
reg [1:0] subfragments_liteethmacsramreader_state = 2'd0;
|
|
reg [1:0] subfragments_liteethmacsramreader_next_state = 2'd0;
|
|
reg [10:0] reader_counter_next_value = 11'd0;
|
|
reg reader_counter_next_value_ce = 1'd0;
|
|
reg [13:0] maccore_maccore_adr = 14'd0;
|
|
reg maccore_maccore_we = 1'd0;
|
|
reg [31:0] maccore_maccore_dat_w = 32'd0;
|
|
wire [31:0] maccore_maccore_dat_r;
|
|
wire [29:0] maccore_maccore_wishbone_adr;
|
|
wire [31:0] maccore_maccore_wishbone_dat_w;
|
|
reg [31:0] maccore_maccore_wishbone_dat_r = 32'd0;
|
|
wire [3:0] maccore_maccore_wishbone_sel;
|
|
wire maccore_maccore_wishbone_cyc;
|
|
wire maccore_maccore_wishbone_stb;
|
|
reg maccore_maccore_wishbone_ack = 1'd0;
|
|
wire maccore_maccore_wishbone_we;
|
|
wire [2:0] maccore_maccore_wishbone_cti;
|
|
wire [1:0] maccore_maccore_wishbone_bte;
|
|
reg maccore_maccore_wishbone_err = 1'd0;
|
|
wire [29:0] maccore_shared_adr;
|
|
wire [31:0] maccore_shared_dat_w;
|
|
reg [31:0] maccore_shared_dat_r = 32'd0;
|
|
wire [3:0] maccore_shared_sel;
|
|
wire maccore_shared_cyc;
|
|
wire maccore_shared_stb;
|
|
reg maccore_shared_ack = 1'd0;
|
|
wire maccore_shared_we;
|
|
wire [2:0] maccore_shared_cti;
|
|
wire [1:0] maccore_shared_bte;
|
|
wire maccore_shared_err;
|
|
wire maccore_request;
|
|
wire maccore_grant;
|
|
reg [1:0] maccore_slave_sel = 2'd0;
|
|
reg [1:0] maccore_slave_sel_r = 2'd0;
|
|
reg maccore_error = 1'd0;
|
|
wire maccore_wait;
|
|
wire maccore_done;
|
|
reg [19:0] maccore_count = 20'd1000000;
|
|
wire [13:0] maccore_interface0_bank_bus_adr;
|
|
wire maccore_interface0_bank_bus_we;
|
|
wire [31:0] maccore_interface0_bank_bus_dat_w;
|
|
reg [31:0] maccore_interface0_bank_bus_dat_r = 32'd0;
|
|
reg maccore_csrbank0_reset0_re = 1'd0;
|
|
wire [1:0] maccore_csrbank0_reset0_r;
|
|
reg maccore_csrbank0_reset0_we = 1'd0;
|
|
wire [1:0] maccore_csrbank0_reset0_w;
|
|
reg maccore_csrbank0_scratch0_re = 1'd0;
|
|
wire [31:0] maccore_csrbank0_scratch0_r;
|
|
reg maccore_csrbank0_scratch0_we = 1'd0;
|
|
wire [31:0] maccore_csrbank0_scratch0_w;
|
|
reg maccore_csrbank0_bus_errors_re = 1'd0;
|
|
wire [31:0] maccore_csrbank0_bus_errors_r;
|
|
reg maccore_csrbank0_bus_errors_we = 1'd0;
|
|
wire [31:0] maccore_csrbank0_bus_errors_w;
|
|
wire maccore_csrbank0_sel;
|
|
wire [13:0] maccore_interface1_bank_bus_adr;
|
|
wire maccore_interface1_bank_bus_we;
|
|
wire [31:0] maccore_interface1_bank_bus_dat_w;
|
|
reg [31:0] maccore_interface1_bank_bus_dat_r = 32'd0;
|
|
reg maccore_csrbank1_sram_writer_slot_re = 1'd0;
|
|
wire maccore_csrbank1_sram_writer_slot_r;
|
|
reg maccore_csrbank1_sram_writer_slot_we = 1'd0;
|
|
wire maccore_csrbank1_sram_writer_slot_w;
|
|
reg maccore_csrbank1_sram_writer_length_re = 1'd0;
|
|
wire [31:0] maccore_csrbank1_sram_writer_length_r;
|
|
reg maccore_csrbank1_sram_writer_length_we = 1'd0;
|
|
wire [31:0] maccore_csrbank1_sram_writer_length_w;
|
|
reg maccore_csrbank1_sram_writer_errors_re = 1'd0;
|
|
wire [31:0] maccore_csrbank1_sram_writer_errors_r;
|
|
reg maccore_csrbank1_sram_writer_errors_we = 1'd0;
|
|
wire [31:0] maccore_csrbank1_sram_writer_errors_w;
|
|
reg maccore_csrbank1_sram_writer_ev_status_re = 1'd0;
|
|
wire maccore_csrbank1_sram_writer_ev_status_r;
|
|
reg maccore_csrbank1_sram_writer_ev_status_we = 1'd0;
|
|
wire maccore_csrbank1_sram_writer_ev_status_w;
|
|
reg maccore_csrbank1_sram_writer_ev_pending_re = 1'd0;
|
|
wire maccore_csrbank1_sram_writer_ev_pending_r;
|
|
reg maccore_csrbank1_sram_writer_ev_pending_we = 1'd0;
|
|
wire maccore_csrbank1_sram_writer_ev_pending_w;
|
|
reg maccore_csrbank1_sram_writer_ev_enable0_re = 1'd0;
|
|
wire maccore_csrbank1_sram_writer_ev_enable0_r;
|
|
reg maccore_csrbank1_sram_writer_ev_enable0_we = 1'd0;
|
|
wire maccore_csrbank1_sram_writer_ev_enable0_w;
|
|
reg maccore_csrbank1_sram_reader_ready_re = 1'd0;
|
|
wire maccore_csrbank1_sram_reader_ready_r;
|
|
reg maccore_csrbank1_sram_reader_ready_we = 1'd0;
|
|
wire maccore_csrbank1_sram_reader_ready_w;
|
|
reg maccore_csrbank1_sram_reader_level_re = 1'd0;
|
|
wire [1:0] maccore_csrbank1_sram_reader_level_r;
|
|
reg maccore_csrbank1_sram_reader_level_we = 1'd0;
|
|
wire [1:0] maccore_csrbank1_sram_reader_level_w;
|
|
reg maccore_csrbank1_sram_reader_slot0_re = 1'd0;
|
|
wire maccore_csrbank1_sram_reader_slot0_r;
|
|
reg maccore_csrbank1_sram_reader_slot0_we = 1'd0;
|
|
wire maccore_csrbank1_sram_reader_slot0_w;
|
|
reg maccore_csrbank1_sram_reader_length0_re = 1'd0;
|
|
wire [10:0] maccore_csrbank1_sram_reader_length0_r;
|
|
reg maccore_csrbank1_sram_reader_length0_we = 1'd0;
|
|
wire [10:0] maccore_csrbank1_sram_reader_length0_w;
|
|
reg maccore_csrbank1_sram_reader_ev_status_re = 1'd0;
|
|
wire maccore_csrbank1_sram_reader_ev_status_r;
|
|
reg maccore_csrbank1_sram_reader_ev_status_we = 1'd0;
|
|
wire maccore_csrbank1_sram_reader_ev_status_w;
|
|
reg maccore_csrbank1_sram_reader_ev_pending_re = 1'd0;
|
|
wire maccore_csrbank1_sram_reader_ev_pending_r;
|
|
reg maccore_csrbank1_sram_reader_ev_pending_we = 1'd0;
|
|
wire maccore_csrbank1_sram_reader_ev_pending_w;
|
|
reg maccore_csrbank1_sram_reader_ev_enable0_re = 1'd0;
|
|
wire maccore_csrbank1_sram_reader_ev_enable0_r;
|
|
reg maccore_csrbank1_sram_reader_ev_enable0_we = 1'd0;
|
|
wire maccore_csrbank1_sram_reader_ev_enable0_w;
|
|
reg maccore_csrbank1_preamble_crc_re = 1'd0;
|
|
wire maccore_csrbank1_preamble_crc_r;
|
|
reg maccore_csrbank1_preamble_crc_we = 1'd0;
|
|
wire maccore_csrbank1_preamble_crc_w;
|
|
reg maccore_csrbank1_preamble_errors_re = 1'd0;
|
|
wire [31:0] maccore_csrbank1_preamble_errors_r;
|
|
reg maccore_csrbank1_preamble_errors_we = 1'd0;
|
|
wire [31:0] maccore_csrbank1_preamble_errors_w;
|
|
reg maccore_csrbank1_crc_errors_re = 1'd0;
|
|
wire [31:0] maccore_csrbank1_crc_errors_r;
|
|
reg maccore_csrbank1_crc_errors_we = 1'd0;
|
|
wire [31:0] maccore_csrbank1_crc_errors_w;
|
|
wire maccore_csrbank1_sel;
|
|
wire [13:0] maccore_interface2_bank_bus_adr;
|
|
wire maccore_interface2_bank_bus_we;
|
|
wire [31:0] maccore_interface2_bank_bus_dat_w;
|
|
reg [31:0] maccore_interface2_bank_bus_dat_r = 32'd0;
|
|
reg maccore_csrbank2_mode_detection_mode_re = 1'd0;
|
|
wire maccore_csrbank2_mode_detection_mode_r;
|
|
reg maccore_csrbank2_mode_detection_mode_we = 1'd0;
|
|
wire maccore_csrbank2_mode_detection_mode_w;
|
|
reg maccore_csrbank2_crg_reset0_re = 1'd0;
|
|
wire maccore_csrbank2_crg_reset0_r;
|
|
reg maccore_csrbank2_crg_reset0_we = 1'd0;
|
|
wire maccore_csrbank2_crg_reset0_w;
|
|
reg maccore_csrbank2_mdio_w0_re = 1'd0;
|
|
wire [2:0] maccore_csrbank2_mdio_w0_r;
|
|
reg maccore_csrbank2_mdio_w0_we = 1'd0;
|
|
wire [2:0] maccore_csrbank2_mdio_w0_w;
|
|
reg maccore_csrbank2_mdio_r_re = 1'd0;
|
|
wire maccore_csrbank2_mdio_r_r;
|
|
reg maccore_csrbank2_mdio_r_we = 1'd0;
|
|
wire maccore_csrbank2_mdio_r_w;
|
|
wire maccore_csrbank2_sel;
|
|
wire [13:0] maccore_csr_interconnect_adr;
|
|
wire maccore_csr_interconnect_we;
|
|
wire [31:0] maccore_csr_interconnect_dat_w;
|
|
wire [31:0] maccore_csr_interconnect_dat_r;
|
|
reg maccore_state = 1'd0;
|
|
reg maccore_next_state = 1'd0;
|
|
reg [29:0] array_muxed0 = 30'd0;
|
|
reg [31:0] array_muxed1 = 32'd0;
|
|
reg [3:0] array_muxed2 = 4'd0;
|
|
reg array_muxed3 = 1'd0;
|
|
reg array_muxed4 = 1'd0;
|
|
reg array_muxed5 = 1'd0;
|
|
reg [2:0] array_muxed6 = 3'd0;
|
|
reg [1:0] array_muxed7 = 2'd0;
|
|
(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl0_regs0 = 1'd0;
|
|
(* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl0_regs1 = 1'd0;
|
|
wire rst_meta0;
|
|
wire rst_meta1;
|
|
(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl1_regs0 = 1'd0;
|
|
(* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl1_regs1 = 1'd0;
|
|
(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl2_regs0 = 1'd0;
|
|
(* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl2_regs1 = 1'd0;
|
|
(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl3_regs0 = 1'd0;
|
|
(* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl3_regs1 = 1'd0;
|
|
(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [5:0] xilinxmultiregimpl4_regs0 = 6'd0;
|
|
(* async_reg = "true", dont_touch = "true" *) reg [5:0] xilinxmultiregimpl4_regs1 = 6'd0;
|
|
(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [5:0] xilinxmultiregimpl5_regs0 = 6'd0;
|
|
(* async_reg = "true", dont_touch = "true" *) reg [5:0] xilinxmultiregimpl5_regs1 = 6'd0;
|
|
(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [5:0] xilinxmultiregimpl6_regs0 = 6'd0;
|
|
(* async_reg = "true", dont_touch = "true" *) reg [5:0] xilinxmultiregimpl6_regs1 = 6'd0;
|
|
(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [5:0] xilinxmultiregimpl7_regs0 = 6'd0;
|
|
(* async_reg = "true", dont_touch = "true" *) reg [5:0] xilinxmultiregimpl7_regs1 = 6'd0;
|
|
|
|
assign wb_bus_adr = wishbone_adr;
|
|
assign wb_bus_dat_w = wishbone_dat_w;
|
|
assign wishbone_dat_r = wb_bus_dat_r;
|
|
assign wb_bus_sel = wishbone_sel;
|
|
assign wb_bus_cyc = wishbone_cyc;
|
|
assign wb_bus_stb = wishbone_stb;
|
|
assign wishbone_ack = wb_bus_ack;
|
|
assign wb_bus_we = wishbone_we;
|
|
assign wb_bus_cti = wishbone_cti;
|
|
assign wb_bus_bte = wishbone_bte;
|
|
assign wishbone_err = wb_bus_err;
|
|
assign interrupt = ev_irq;
|
|
assign maccore_maccore_bus_error = maccore_error;
|
|
assign maccore_maccore_bus_errors_status = maccore_maccore_bus_errors;
|
|
assign sys_clk = sys_clock;
|
|
assign por_clk = sys_clock;
|
|
assign sys_rst = maccore_int_rst;
|
|
assign maccore_ethphy_mode_status = maccore_ethphy_mode0;
|
|
assign maccore_ethphy_eth_tick = (maccore_ethphy_eth_counter == 1'd0);
|
|
assign maccore_ethphy_i = maccore_ethphy_eth_tick;
|
|
assign maccore_ethphy_sys_tick = maccore_ethphy_o;
|
|
assign maccore_ethphy_o = (maccore_ethphy_toggle_o ^ maccore_ethphy_toggle_o_r);
|
|
always @(*) begin
|
|
subfragments_next_state <= 2'd0;
|
|
maccore_ethphy_sys_counter_reset <= 1'd0;
|
|
maccore_ethphy_sys_counter_ce <= 1'd0;
|
|
maccore_ethphy_mode1 <= 1'd0;
|
|
maccore_ethphy_update_mode <= 1'd0;
|
|
subfragments_next_state <= subfragments_state;
|
|
case (subfragments_state)
|
|
1'd1: begin
|
|
maccore_ethphy_sys_counter_ce <= 1'd1;
|
|
if (maccore_ethphy_sys_tick) begin
|
|
subfragments_next_state <= 2'd2;
|
|
end
|
|
end
|
|
2'd2: begin
|
|
maccore_ethphy_update_mode <= 1'd1;
|
|
if ((maccore_ethphy_sys_counter > 10'd860)) begin
|
|
maccore_ethphy_mode1 <= 1'd1;
|
|
end else begin
|
|
maccore_ethphy_mode1 <= 1'd0;
|
|
end
|
|
subfragments_next_state <= 1'd0;
|
|
end
|
|
default: begin
|
|
maccore_ethphy_sys_counter_reset <= 1'd1;
|
|
if (maccore_ethphy_sys_tick) begin
|
|
subfragments_next_state <= 1'd1;
|
|
end
|
|
end
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
maccore_ethphy_eth_tx_clk <= 1'd0;
|
|
if ((maccore_ethphy_mode0 == 1'd1)) begin
|
|
maccore_ethphy_eth_tx_clk <= gmii_eth_clocks_tx;
|
|
end else begin
|
|
maccore_ethphy_eth_tx_clk <= gmii_eth_clocks_rx;
|
|
end
|
|
end
|
|
assign maccore_ethphy_reset0 = (maccore_ethphy_reset_storage | maccore_ethphy_reset1);
|
|
assign gmii_eth_rst_n = (~maccore_ethphy_reset0);
|
|
assign maccore_ethphy_counter_done = (maccore_ethphy_counter == 9'd256);
|
|
assign maccore_ethphy_counter_ce = (~maccore_ethphy_counter_done);
|
|
assign maccore_ethphy_reset1 = (~maccore_ethphy_counter_done);
|
|
assign maccore_ethphy_liteethphygmiimiitx_demux_sel = (maccore_ethphy_mode0 == 1'd1);
|
|
assign maccore_ethphy_liteethphygmiimiitx_demux_sink_valid = maccore_ethphy_liteethphygmiimiitx_sink_sink_valid0;
|
|
assign maccore_ethphy_liteethphygmiimiitx_sink_sink_ready0 = maccore_ethphy_liteethphygmiimiitx_demux_sink_ready;
|
|
assign maccore_ethphy_liteethphygmiimiitx_demux_sink_first = maccore_ethphy_liteethphygmiimiitx_sink_sink_first0;
|
|
assign maccore_ethphy_liteethphygmiimiitx_demux_sink_last = maccore_ethphy_liteethphygmiimiitx_sink_sink_last0;
|
|
assign maccore_ethphy_liteethphygmiimiitx_demux_sink_payload_data = maccore_ethphy_liteethphygmiimiitx_sink_sink_payload_data0;
|
|
assign maccore_ethphy_liteethphygmiimiitx_demux_sink_payload_last_be = maccore_ethphy_liteethphygmiimiitx_sink_sink_payload_last_be0;
|
|
assign maccore_ethphy_liteethphygmiimiitx_demux_sink_payload_error = maccore_ethphy_liteethphygmiimiitx_sink_sink_payload_error0;
|
|
assign maccore_ethphy_liteethphygmiimiitx_gmii_tx_sink_valid = maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_valid;
|
|
assign maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_ready = maccore_ethphy_liteethphygmiimiitx_gmii_tx_sink_ready;
|
|
assign maccore_ethphy_liteethphygmiimiitx_gmii_tx_sink_first = maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_first;
|
|
assign maccore_ethphy_liteethphygmiimiitx_gmii_tx_sink_last = maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_last;
|
|
assign maccore_ethphy_liteethphygmiimiitx_gmii_tx_sink_payload_data = maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_payload_data;
|
|
assign maccore_ethphy_liteethphygmiimiitx_gmii_tx_sink_payload_last_be = maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_payload_last_be;
|
|
assign maccore_ethphy_liteethphygmiimiitx_gmii_tx_sink_payload_error = maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_payload_error;
|
|
assign maccore_ethphy_liteethphygmiimiitx_sink_sink_valid1 = maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_valid;
|
|
assign maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_ready = maccore_ethphy_liteethphygmiimiitx_sink_sink_ready1;
|
|
assign maccore_ethphy_liteethphygmiimiitx_sink_sink_first1 = maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_first;
|
|
assign maccore_ethphy_liteethphygmiimiitx_sink_sink_last1 = maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_last;
|
|
assign maccore_ethphy_liteethphygmiimiitx_sink_sink_payload_data1 = maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_payload_data;
|
|
assign maccore_ethphy_liteethphygmiimiitx_sink_sink_payload_last_be1 = maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_payload_last_be;
|
|
assign maccore_ethphy_liteethphygmiimiitx_sink_sink_payload_error1 = maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_payload_error;
|
|
assign gmii_eth_tx_er = 1'd0;
|
|
assign maccore_ethphy_liteethphygmiimiitx_converter_sink_valid = maccore_ethphy_liteethphygmiimiitx_sink_sink_valid1;
|
|
assign maccore_ethphy_liteethphygmiimiitx_converter_sink_payload_data = maccore_ethphy_liteethphygmiimiitx_sink_sink_payload_data1;
|
|
assign maccore_ethphy_liteethphygmiimiitx_sink_sink_ready1 = maccore_ethphy_liteethphygmiimiitx_converter_sink_ready;
|
|
assign maccore_ethphy_liteethphygmiimiitx_converter_source_ready = 1'd1;
|
|
assign maccore_ethphy_liteethphygmiimiitx_converter_converter_sink_valid = maccore_ethphy_liteethphygmiimiitx_converter_sink_valid;
|
|
assign maccore_ethphy_liteethphygmiimiitx_converter_converter_sink_first = maccore_ethphy_liteethphygmiimiitx_converter_sink_first;
|
|
assign maccore_ethphy_liteethphygmiimiitx_converter_converter_sink_last = maccore_ethphy_liteethphygmiimiitx_converter_sink_last;
|
|
assign maccore_ethphy_liteethphygmiimiitx_converter_sink_ready = maccore_ethphy_liteethphygmiimiitx_converter_converter_sink_ready;
|
|
always @(*) begin
|
|
maccore_ethphy_liteethphygmiimiitx_converter_converter_sink_payload_data <= 8'd0;
|
|
maccore_ethphy_liteethphygmiimiitx_converter_converter_sink_payload_data[3:0] <= maccore_ethphy_liteethphygmiimiitx_converter_sink_payload_data[3:0];
|
|
maccore_ethphy_liteethphygmiimiitx_converter_converter_sink_payload_data[7:4] <= maccore_ethphy_liteethphygmiimiitx_converter_sink_payload_data[7:4];
|
|
end
|
|
assign maccore_ethphy_liteethphygmiimiitx_converter_source_valid = maccore_ethphy_liteethphygmiimiitx_converter_source_source_valid;
|
|
assign maccore_ethphy_liteethphygmiimiitx_converter_source_first = maccore_ethphy_liteethphygmiimiitx_converter_source_source_first;
|
|
assign maccore_ethphy_liteethphygmiimiitx_converter_source_last = maccore_ethphy_liteethphygmiimiitx_converter_source_source_last;
|
|
assign maccore_ethphy_liteethphygmiimiitx_converter_source_source_ready = maccore_ethphy_liteethphygmiimiitx_converter_source_ready;
|
|
assign {maccore_ethphy_liteethphygmiimiitx_converter_source_payload_data} = maccore_ethphy_liteethphygmiimiitx_converter_source_source_payload_data;
|
|
assign maccore_ethphy_liteethphygmiimiitx_converter_source_source_valid = maccore_ethphy_liteethphygmiimiitx_converter_converter_source_valid;
|
|
assign maccore_ethphy_liteethphygmiimiitx_converter_converter_source_ready = maccore_ethphy_liteethphygmiimiitx_converter_source_source_ready;
|
|
assign maccore_ethphy_liteethphygmiimiitx_converter_source_source_first = maccore_ethphy_liteethphygmiimiitx_converter_converter_source_first;
|
|
assign maccore_ethphy_liteethphygmiimiitx_converter_source_source_last = maccore_ethphy_liteethphygmiimiitx_converter_converter_source_last;
|
|
assign maccore_ethphy_liteethphygmiimiitx_converter_source_source_payload_data = maccore_ethphy_liteethphygmiimiitx_converter_converter_source_payload_data;
|
|
assign maccore_ethphy_liteethphygmiimiitx_converter_converter_first = (maccore_ethphy_liteethphygmiimiitx_converter_converter_mux == 1'd0);
|
|
assign maccore_ethphy_liteethphygmiimiitx_converter_converter_last = (maccore_ethphy_liteethphygmiimiitx_converter_converter_mux == 1'd1);
|
|
assign maccore_ethphy_liteethphygmiimiitx_converter_converter_source_valid = maccore_ethphy_liteethphygmiimiitx_converter_converter_sink_valid;
|
|
assign maccore_ethphy_liteethphygmiimiitx_converter_converter_source_first = (maccore_ethphy_liteethphygmiimiitx_converter_converter_sink_first & maccore_ethphy_liteethphygmiimiitx_converter_converter_first);
|
|
assign maccore_ethphy_liteethphygmiimiitx_converter_converter_source_last = (maccore_ethphy_liteethphygmiimiitx_converter_converter_sink_last & maccore_ethphy_liteethphygmiimiitx_converter_converter_last);
|
|
assign maccore_ethphy_liteethphygmiimiitx_converter_converter_sink_ready = (maccore_ethphy_liteethphygmiimiitx_converter_converter_last & maccore_ethphy_liteethphygmiimiitx_converter_converter_source_ready);
|
|
always @(*) begin
|
|
maccore_ethphy_liteethphygmiimiitx_converter_converter_source_payload_data <= 4'd0;
|
|
case (maccore_ethphy_liteethphygmiimiitx_converter_converter_mux)
|
|
1'd0: begin
|
|
maccore_ethphy_liteethphygmiimiitx_converter_converter_source_payload_data <= maccore_ethphy_liteethphygmiimiitx_converter_converter_sink_payload_data[3:0];
|
|
end
|
|
default: begin
|
|
maccore_ethphy_liteethphygmiimiitx_converter_converter_source_payload_data <= maccore_ethphy_liteethphygmiimiitx_converter_converter_sink_payload_data[7:4];
|
|
end
|
|
endcase
|
|
end
|
|
assign maccore_ethphy_liteethphygmiimiitx_converter_converter_source_payload_valid_token_count = maccore_ethphy_liteethphygmiimiitx_converter_converter_last;
|
|
always @(*) begin
|
|
maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_payload_data <= 8'd0;
|
|
maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_last <= 1'd0;
|
|
maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_payload_last_be <= 1'd0;
|
|
maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_payload_error <= 1'd0;
|
|
maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_valid <= 1'd0;
|
|
maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_first <= 1'd0;
|
|
maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_last <= 1'd0;
|
|
maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_payload_data <= 8'd0;
|
|
maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_payload_last_be <= 1'd0;
|
|
maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_payload_error <= 1'd0;
|
|
maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_valid <= 1'd0;
|
|
maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_first <= 1'd0;
|
|
maccore_ethphy_liteethphygmiimiitx_demux_sink_ready <= 1'd0;
|
|
case (maccore_ethphy_liteethphygmiimiitx_demux_sel)
|
|
1'd0: begin
|
|
maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_valid <= maccore_ethphy_liteethphygmiimiitx_demux_sink_valid;
|
|
maccore_ethphy_liteethphygmiimiitx_demux_sink_ready <= maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_ready;
|
|
maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_first <= maccore_ethphy_liteethphygmiimiitx_demux_sink_first;
|
|
maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_last <= maccore_ethphy_liteethphygmiimiitx_demux_sink_last;
|
|
maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_payload_data <= maccore_ethphy_liteethphygmiimiitx_demux_sink_payload_data;
|
|
maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_payload_last_be <= maccore_ethphy_liteethphygmiimiitx_demux_sink_payload_last_be;
|
|
maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_payload_error <= maccore_ethphy_liteethphygmiimiitx_demux_sink_payload_error;
|
|
end
|
|
1'd1: begin
|
|
maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_valid <= maccore_ethphy_liteethphygmiimiitx_demux_sink_valid;
|
|
maccore_ethphy_liteethphygmiimiitx_demux_sink_ready <= maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_ready;
|
|
maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_first <= maccore_ethphy_liteethphygmiimiitx_demux_sink_first;
|
|
maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_last <= maccore_ethphy_liteethphygmiimiitx_demux_sink_last;
|
|
maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_payload_data <= maccore_ethphy_liteethphygmiimiitx_demux_sink_payload_data;
|
|
maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_payload_last_be <= maccore_ethphy_liteethphygmiimiitx_demux_sink_payload_last_be;
|
|
maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_payload_error <= maccore_ethphy_liteethphygmiimiitx_demux_sink_payload_error;
|
|
end
|
|
endcase
|
|
end
|
|
assign maccore_ethphy_liteethphygmiimiirx_mux_sel = (maccore_ethphy_mode0 == 1'd1);
|
|
assign maccore_ethphy_liteethphygmiimiirx_mux_endpoint0_sink_valid = maccore_ethphy_liteethphygmiimiirx_gmii_rx_source_valid;
|
|
assign maccore_ethphy_liteethphygmiimiirx_gmii_rx_source_ready = maccore_ethphy_liteethphygmiimiirx_mux_endpoint0_sink_ready;
|
|
assign maccore_ethphy_liteethphygmiimiirx_mux_endpoint0_sink_first = maccore_ethphy_liteethphygmiimiirx_gmii_rx_source_first;
|
|
assign maccore_ethphy_liteethphygmiimiirx_mux_endpoint0_sink_last = maccore_ethphy_liteethphygmiimiirx_gmii_rx_source_last;
|
|
assign maccore_ethphy_liteethphygmiimiirx_mux_endpoint0_sink_payload_data = maccore_ethphy_liteethphygmiimiirx_gmii_rx_source_payload_data;
|
|
assign maccore_ethphy_liteethphygmiimiirx_mux_endpoint0_sink_payload_last_be = maccore_ethphy_liteethphygmiimiirx_gmii_rx_source_payload_last_be;
|
|
assign maccore_ethphy_liteethphygmiimiirx_mux_endpoint0_sink_payload_error = maccore_ethphy_liteethphygmiimiirx_gmii_rx_source_payload_error;
|
|
assign maccore_ethphy_liteethphygmiimiirx_mux_endpoint1_sink_valid = maccore_ethphy_liteethphygmiimiirx_source_source_valid1;
|
|
assign maccore_ethphy_liteethphygmiimiirx_source_source_ready1 = maccore_ethphy_liteethphygmiimiirx_mux_endpoint1_sink_ready;
|
|
assign maccore_ethphy_liteethphygmiimiirx_mux_endpoint1_sink_first = maccore_ethphy_liteethphygmiimiirx_source_source_first1;
|
|
assign maccore_ethphy_liteethphygmiimiirx_mux_endpoint1_sink_last = maccore_ethphy_liteethphygmiimiirx_source_source_last1;
|
|
assign maccore_ethphy_liteethphygmiimiirx_mux_endpoint1_sink_payload_data = maccore_ethphy_liteethphygmiimiirx_source_source_payload_data1;
|
|
assign maccore_ethphy_liteethphygmiimiirx_mux_endpoint1_sink_payload_last_be = maccore_ethphy_liteethphygmiimiirx_source_source_payload_last_be1;
|
|
assign maccore_ethphy_liteethphygmiimiirx_mux_endpoint1_sink_payload_error = maccore_ethphy_liteethphygmiimiirx_source_source_payload_error1;
|
|
assign maccore_ethphy_liteethphygmiimiirx_source_source_valid0 = maccore_ethphy_liteethphygmiimiirx_mux_source_valid;
|
|
assign maccore_ethphy_liteethphygmiimiirx_mux_source_ready = maccore_ethphy_liteethphygmiimiirx_source_source_ready0;
|
|
assign maccore_ethphy_liteethphygmiimiirx_source_source_first0 = maccore_ethphy_liteethphygmiimiirx_mux_source_first;
|
|
assign maccore_ethphy_liteethphygmiimiirx_source_source_last0 = maccore_ethphy_liteethphygmiimiirx_mux_source_last;
|
|
assign maccore_ethphy_liteethphygmiimiirx_source_source_payload_data0 = maccore_ethphy_liteethphygmiimiirx_mux_source_payload_data;
|
|
assign maccore_ethphy_liteethphygmiimiirx_source_source_payload_last_be0 = maccore_ethphy_liteethphygmiimiirx_mux_source_payload_last_be;
|
|
assign maccore_ethphy_liteethphygmiimiirx_source_source_payload_error0 = maccore_ethphy_liteethphygmiimiirx_mux_source_payload_error;
|
|
assign maccore_ethphy_liteethphygmiimiirx_gmii_rx_source_last = ((~maccore_ethphy_liteethphygmiimiirx_pads_d_rx_dv) & maccore_ethphy_liteethphygmiimiirx_gmii_rx_dv_d);
|
|
assign maccore_ethphy_liteethphygmiimiirx_converter_sink_last = (~maccore_ethphy_liteethphygmiimiirx_pads_d_rx_dv);
|
|
assign maccore_ethphy_liteethphygmiimiirx_source_source_valid1 = maccore_ethphy_liteethphygmiimiirx_converter_source_valid;
|
|
assign maccore_ethphy_liteethphygmiimiirx_converter_source_ready = maccore_ethphy_liteethphygmiimiirx_source_source_ready1;
|
|
assign maccore_ethphy_liteethphygmiimiirx_source_source_first1 = maccore_ethphy_liteethphygmiimiirx_converter_source_first;
|
|
assign maccore_ethphy_liteethphygmiimiirx_source_source_last1 = maccore_ethphy_liteethphygmiimiirx_converter_source_last;
|
|
assign maccore_ethphy_liteethphygmiimiirx_source_source_payload_data1 = maccore_ethphy_liteethphygmiimiirx_converter_source_payload_data;
|
|
assign maccore_ethphy_liteethphygmiimiirx_converter_converter_sink_valid = maccore_ethphy_liteethphygmiimiirx_converter_sink_valid;
|
|
assign maccore_ethphy_liteethphygmiimiirx_converter_converter_sink_first = maccore_ethphy_liteethphygmiimiirx_converter_sink_first;
|
|
assign maccore_ethphy_liteethphygmiimiirx_converter_converter_sink_last = maccore_ethphy_liteethphygmiimiirx_converter_sink_last;
|
|
assign maccore_ethphy_liteethphygmiimiirx_converter_sink_ready = maccore_ethphy_liteethphygmiimiirx_converter_converter_sink_ready;
|
|
assign maccore_ethphy_liteethphygmiimiirx_converter_converter_sink_payload_data = {maccore_ethphy_liteethphygmiimiirx_converter_sink_payload_data};
|
|
assign maccore_ethphy_liteethphygmiimiirx_converter_source_valid = maccore_ethphy_liteethphygmiimiirx_converter_source_source_valid;
|
|
assign maccore_ethphy_liteethphygmiimiirx_converter_source_first = maccore_ethphy_liteethphygmiimiirx_converter_source_source_first;
|
|
assign maccore_ethphy_liteethphygmiimiirx_converter_source_last = maccore_ethphy_liteethphygmiimiirx_converter_source_source_last;
|
|
assign maccore_ethphy_liteethphygmiimiirx_converter_source_source_ready = maccore_ethphy_liteethphygmiimiirx_converter_source_ready;
|
|
always @(*) begin
|
|
maccore_ethphy_liteethphygmiimiirx_converter_source_payload_data <= 8'd0;
|
|
maccore_ethphy_liteethphygmiimiirx_converter_source_payload_data[3:0] <= maccore_ethphy_liteethphygmiimiirx_converter_source_source_payload_data[3:0];
|
|
maccore_ethphy_liteethphygmiimiirx_converter_source_payload_data[7:4] <= maccore_ethphy_liteethphygmiimiirx_converter_source_source_payload_data[7:4];
|
|
end
|
|
assign maccore_ethphy_liteethphygmiimiirx_converter_source_source_valid = maccore_ethphy_liteethphygmiimiirx_converter_converter_source_valid;
|
|
assign maccore_ethphy_liteethphygmiimiirx_converter_converter_source_ready = maccore_ethphy_liteethphygmiimiirx_converter_source_source_ready;
|
|
assign maccore_ethphy_liteethphygmiimiirx_converter_source_source_first = maccore_ethphy_liteethphygmiimiirx_converter_converter_source_first;
|
|
assign maccore_ethphy_liteethphygmiimiirx_converter_source_source_last = maccore_ethphy_liteethphygmiimiirx_converter_converter_source_last;
|
|
assign maccore_ethphy_liteethphygmiimiirx_converter_source_source_payload_data = maccore_ethphy_liteethphygmiimiirx_converter_converter_source_payload_data;
|
|
assign maccore_ethphy_liteethphygmiimiirx_converter_converter_sink_ready = ((~maccore_ethphy_liteethphygmiimiirx_converter_converter_strobe_all) | maccore_ethphy_liteethphygmiimiirx_converter_converter_source_ready);
|
|
assign maccore_ethphy_liteethphygmiimiirx_converter_converter_source_valid = maccore_ethphy_liteethphygmiimiirx_converter_converter_strobe_all;
|
|
assign maccore_ethphy_liteethphygmiimiirx_converter_converter_load_part = (maccore_ethphy_liteethphygmiimiirx_converter_converter_sink_valid & maccore_ethphy_liteethphygmiimiirx_converter_converter_sink_ready);
|
|
always @(*) begin
|
|
maccore_ethphy_liteethphygmiimiirx_mux_source_valid <= 1'd0;
|
|
maccore_ethphy_liteethphygmiimiirx_mux_source_first <= 1'd0;
|
|
maccore_ethphy_liteethphygmiimiirx_mux_source_last <= 1'd0;
|
|
maccore_ethphy_liteethphygmiimiirx_mux_source_payload_data <= 8'd0;
|
|
maccore_ethphy_liteethphygmiimiirx_mux_source_payload_last_be <= 1'd0;
|
|
maccore_ethphy_liteethphygmiimiirx_mux_source_payload_error <= 1'd0;
|
|
maccore_ethphy_liteethphygmiimiirx_mux_endpoint0_sink_ready <= 1'd0;
|
|
maccore_ethphy_liteethphygmiimiirx_mux_endpoint1_sink_ready <= 1'd0;
|
|
case (maccore_ethphy_liteethphygmiimiirx_mux_sel)
|
|
1'd0: begin
|
|
maccore_ethphy_liteethphygmiimiirx_mux_source_valid <= maccore_ethphy_liteethphygmiimiirx_mux_endpoint0_sink_valid;
|
|
maccore_ethphy_liteethphygmiimiirx_mux_endpoint0_sink_ready <= maccore_ethphy_liteethphygmiimiirx_mux_source_ready;
|
|
maccore_ethphy_liteethphygmiimiirx_mux_source_first <= maccore_ethphy_liteethphygmiimiirx_mux_endpoint0_sink_first;
|
|
maccore_ethphy_liteethphygmiimiirx_mux_source_last <= maccore_ethphy_liteethphygmiimiirx_mux_endpoint0_sink_last;
|
|
maccore_ethphy_liteethphygmiimiirx_mux_source_payload_data <= maccore_ethphy_liteethphygmiimiirx_mux_endpoint0_sink_payload_data;
|
|
maccore_ethphy_liteethphygmiimiirx_mux_source_payload_last_be <= maccore_ethphy_liteethphygmiimiirx_mux_endpoint0_sink_payload_last_be;
|
|
maccore_ethphy_liteethphygmiimiirx_mux_source_payload_error <= maccore_ethphy_liteethphygmiimiirx_mux_endpoint0_sink_payload_error;
|
|
end
|
|
1'd1: begin
|
|
maccore_ethphy_liteethphygmiimiirx_mux_source_valid <= maccore_ethphy_liteethphygmiimiirx_mux_endpoint1_sink_valid;
|
|
maccore_ethphy_liteethphygmiimiirx_mux_endpoint1_sink_ready <= maccore_ethphy_liteethphygmiimiirx_mux_source_ready;
|
|
maccore_ethphy_liteethphygmiimiirx_mux_source_first <= maccore_ethphy_liteethphygmiimiirx_mux_endpoint1_sink_first;
|
|
maccore_ethphy_liteethphygmiimiirx_mux_source_last <= maccore_ethphy_liteethphygmiimiirx_mux_endpoint1_sink_last;
|
|
maccore_ethphy_liteethphygmiimiirx_mux_source_payload_data <= maccore_ethphy_liteethphygmiimiirx_mux_endpoint1_sink_payload_data;
|
|
maccore_ethphy_liteethphygmiimiirx_mux_source_payload_last_be <= maccore_ethphy_liteethphygmiimiirx_mux_endpoint1_sink_payload_last_be;
|
|
maccore_ethphy_liteethphygmiimiirx_mux_source_payload_error <= maccore_ethphy_liteethphygmiimiirx_mux_endpoint1_sink_payload_error;
|
|
end
|
|
endcase
|
|
end
|
|
assign gmii_eth_mdc = maccore_ethphy__w_storage[0];
|
|
assign maccore_ethphy_data_oe = maccore_ethphy__w_storage[1];
|
|
assign maccore_ethphy_data_w = maccore_ethphy__w_storage[2];
|
|
assign tx_cdc_sink_sink_valid = source_valid;
|
|
assign source_ready = tx_cdc_sink_sink_ready;
|
|
assign tx_cdc_sink_sink_first = source_first;
|
|
assign tx_cdc_sink_sink_last = source_last;
|
|
assign tx_cdc_sink_sink_payload_data = source_payload_data;
|
|
assign tx_cdc_sink_sink_payload_last_be = source_payload_last_be;
|
|
assign tx_cdc_sink_sink_payload_error = source_payload_error;
|
|
assign sink_valid = rx_cdc_source_source_valid;
|
|
assign rx_cdc_source_source_ready = sink_ready;
|
|
assign sink_first = rx_cdc_source_source_first;
|
|
assign sink_last = rx_cdc_source_source_last;
|
|
assign sink_payload_data = rx_cdc_source_source_payload_data;
|
|
assign sink_payload_last_be = rx_cdc_source_source_payload_last_be;
|
|
assign sink_payload_error = rx_cdc_source_source_payload_error;
|
|
assign ps_preamble_error_i = preamble_checker_error;
|
|
assign ps_crc_error_i = liteethmaccrc32checker_error;
|
|
always @(*) begin
|
|
tx_gap_inserter_source_valid <= 1'd0;
|
|
tx_gap_inserter_source_first <= 1'd0;
|
|
tx_gap_inserter_source_last <= 1'd0;
|
|
tx_gap_inserter_source_payload_data <= 8'd0;
|
|
tx_gap_inserter_source_payload_last_be <= 1'd0;
|
|
tx_gap_inserter_source_payload_error <= 1'd0;
|
|
subfragments_liteethmacgap_next_state <= 1'd0;
|
|
tx_gap_inserter_counter_liteethmacgap_next_value <= 4'd0;
|
|
tx_gap_inserter_counter_liteethmacgap_next_value_ce <= 1'd0;
|
|
tx_gap_inserter_sink_ready <= 1'd0;
|
|
subfragments_liteethmacgap_next_state <= subfragments_liteethmacgap_state;
|
|
case (subfragments_liteethmacgap_state)
|
|
1'd1: begin
|
|
tx_gap_inserter_counter_liteethmacgap_next_value <= (tx_gap_inserter_counter + 1'd1);
|
|
tx_gap_inserter_counter_liteethmacgap_next_value_ce <= 1'd1;
|
|
if ((tx_gap_inserter_counter == 4'd11)) begin
|
|
subfragments_liteethmacgap_next_state <= 1'd0;
|
|
end
|
|
end
|
|
default: begin
|
|
tx_gap_inserter_counter_liteethmacgap_next_value <= 1'd0;
|
|
tx_gap_inserter_counter_liteethmacgap_next_value_ce <= 1'd1;
|
|
tx_gap_inserter_source_valid <= tx_gap_inserter_sink_valid;
|
|
tx_gap_inserter_sink_ready <= tx_gap_inserter_source_ready;
|
|
tx_gap_inserter_source_first <= tx_gap_inserter_sink_first;
|
|
tx_gap_inserter_source_last <= tx_gap_inserter_sink_last;
|
|
tx_gap_inserter_source_payload_data <= tx_gap_inserter_sink_payload_data;
|
|
tx_gap_inserter_source_payload_last_be <= tx_gap_inserter_sink_payload_last_be;
|
|
tx_gap_inserter_source_payload_error <= tx_gap_inserter_sink_payload_error;
|
|
if (((tx_gap_inserter_sink_valid & tx_gap_inserter_sink_last) & tx_gap_inserter_sink_ready)) begin
|
|
subfragments_liteethmacgap_next_state <= 1'd1;
|
|
end
|
|
end
|
|
endcase
|
|
end
|
|
assign preamble_inserter_source_payload_last_be = preamble_inserter_sink_payload_last_be;
|
|
always @(*) begin
|
|
preamble_inserter_source_first <= 1'd0;
|
|
preamble_inserter_source_last <= 1'd0;
|
|
preamble_inserter_source_payload_data <= 8'd0;
|
|
subfragments_liteethmacpreambleinserter_next_state <= 2'd0;
|
|
preamble_inserter_source_payload_error <= 1'd0;
|
|
preamble_inserter_count_liteethmacpreambleinserter_next_value <= 3'd0;
|
|
preamble_inserter_count_liteethmacpreambleinserter_next_value_ce <= 1'd0;
|
|
preamble_inserter_sink_ready <= 1'd0;
|
|
preamble_inserter_source_valid <= 1'd0;
|
|
preamble_inserter_source_payload_data <= preamble_inserter_sink_payload_data;
|
|
subfragments_liteethmacpreambleinserter_next_state <= subfragments_liteethmacpreambleinserter_state;
|
|
case (subfragments_liteethmacpreambleinserter_state)
|
|
1'd1: begin
|
|
preamble_inserter_source_valid <= 1'd1;
|
|
case (preamble_inserter_count)
|
|
1'd0: begin
|
|
preamble_inserter_source_payload_data <= preamble_inserter_preamble[7:0];
|
|
end
|
|
1'd1: begin
|
|
preamble_inserter_source_payload_data <= preamble_inserter_preamble[15:8];
|
|
end
|
|
2'd2: begin
|
|
preamble_inserter_source_payload_data <= preamble_inserter_preamble[23:16];
|
|
end
|
|
2'd3: begin
|
|
preamble_inserter_source_payload_data <= preamble_inserter_preamble[31:24];
|
|
end
|
|
3'd4: begin
|
|
preamble_inserter_source_payload_data <= preamble_inserter_preamble[39:32];
|
|
end
|
|
3'd5: begin
|
|
preamble_inserter_source_payload_data <= preamble_inserter_preamble[47:40];
|
|
end
|
|
3'd6: begin
|
|
preamble_inserter_source_payload_data <= preamble_inserter_preamble[55:48];
|
|
end
|
|
default: begin
|
|
preamble_inserter_source_payload_data <= preamble_inserter_preamble[63:56];
|
|
end
|
|
endcase
|
|
if (preamble_inserter_source_ready) begin
|
|
if ((preamble_inserter_count == 3'd7)) begin
|
|
subfragments_liteethmacpreambleinserter_next_state <= 2'd2;
|
|
end else begin
|
|
preamble_inserter_count_liteethmacpreambleinserter_next_value <= (preamble_inserter_count + 1'd1);
|
|
preamble_inserter_count_liteethmacpreambleinserter_next_value_ce <= 1'd1;
|
|
end
|
|
end
|
|
end
|
|
2'd2: begin
|
|
preamble_inserter_source_valid <= preamble_inserter_sink_valid;
|
|
preamble_inserter_sink_ready <= preamble_inserter_source_ready;
|
|
preamble_inserter_source_first <= preamble_inserter_sink_first;
|
|
preamble_inserter_source_last <= preamble_inserter_sink_last;
|
|
preamble_inserter_source_payload_error <= preamble_inserter_sink_payload_error;
|
|
if (((preamble_inserter_sink_valid & preamble_inserter_sink_last) & preamble_inserter_source_ready)) begin
|
|
subfragments_liteethmacpreambleinserter_next_state <= 1'd0;
|
|
end
|
|
end
|
|
default: begin
|
|
preamble_inserter_sink_ready <= 1'd1;
|
|
preamble_inserter_count_liteethmacpreambleinserter_next_value <= 1'd0;
|
|
preamble_inserter_count_liteethmacpreambleinserter_next_value_ce <= 1'd1;
|
|
if (preamble_inserter_sink_valid) begin
|
|
preamble_inserter_sink_ready <= 1'd0;
|
|
subfragments_liteethmacpreambleinserter_next_state <= 1'd1;
|
|
end
|
|
end
|
|
endcase
|
|
end
|
|
assign preamble_checker_source_payload_data = preamble_checker_sink_payload_data;
|
|
assign preamble_checker_source_payload_last_be = preamble_checker_sink_payload_last_be;
|
|
always @(*) begin
|
|
preamble_checker_source_payload_error <= 1'd0;
|
|
preamble_checker_error <= 1'd0;
|
|
preamble_checker_source_first <= 1'd0;
|
|
preamble_checker_source_valid <= 1'd0;
|
|
subfragments_liteethmacpreamblechecker_next_state <= 1'd0;
|
|
preamble_checker_sink_ready <= 1'd0;
|
|
preamble_checker_source_last <= 1'd0;
|
|
subfragments_liteethmacpreamblechecker_next_state <= subfragments_liteethmacpreamblechecker_state;
|
|
case (subfragments_liteethmacpreamblechecker_state)
|
|
1'd1: begin
|
|
preamble_checker_source_valid <= preamble_checker_sink_valid;
|
|
preamble_checker_sink_ready <= preamble_checker_source_ready;
|
|
preamble_checker_source_first <= preamble_checker_sink_first;
|
|
preamble_checker_source_last <= preamble_checker_sink_last;
|
|
preamble_checker_source_payload_error <= preamble_checker_sink_payload_error;
|
|
if (((preamble_checker_source_valid & preamble_checker_source_last) & preamble_checker_source_ready)) begin
|
|
subfragments_liteethmacpreamblechecker_next_state <= 1'd0;
|
|
end
|
|
end
|
|
default: begin
|
|
preamble_checker_sink_ready <= 1'd1;
|
|
if (((preamble_checker_sink_valid & (~preamble_checker_sink_last)) & (preamble_checker_sink_payload_data == 8'd213))) begin
|
|
subfragments_liteethmacpreamblechecker_next_state <= 1'd1;
|
|
end
|
|
if ((preamble_checker_sink_valid & preamble_checker_sink_last)) begin
|
|
preamble_checker_error <= 1'd1;
|
|
end
|
|
end
|
|
endcase
|
|
end
|
|
assign liteethmaccrc32inserter_cnt_done = (liteethmaccrc32inserter_cnt == 1'd0);
|
|
assign liteethmaccrc32inserter_sink_valid = crc32_inserter_source_valid;
|
|
assign crc32_inserter_source_ready = liteethmaccrc32inserter_sink_ready;
|
|
assign liteethmaccrc32inserter_sink_first = crc32_inserter_source_first;
|
|
assign liteethmaccrc32inserter_sink_last = crc32_inserter_source_last;
|
|
assign liteethmaccrc32inserter_sink_payload_data = crc32_inserter_source_payload_data;
|
|
assign liteethmaccrc32inserter_sink_payload_last_be = crc32_inserter_source_payload_last_be;
|
|
assign liteethmaccrc32inserter_sink_payload_error = crc32_inserter_source_payload_error;
|
|
assign liteethmaccrc32inserter_data1 = liteethmaccrc32inserter_data0;
|
|
assign liteethmaccrc32inserter_last = liteethmaccrc32inserter_reg;
|
|
assign liteethmaccrc32inserter_value = (~{liteethmaccrc32inserter_reg[0], liteethmaccrc32inserter_reg[1], liteethmaccrc32inserter_reg[2], liteethmaccrc32inserter_reg[3], liteethmaccrc32inserter_reg[4], liteethmaccrc32inserter_reg[5], liteethmaccrc32inserter_reg[6], liteethmaccrc32inserter_reg[7], liteethmaccrc32inserter_reg[8], liteethmaccrc32inserter_reg[9], liteethmaccrc32inserter_reg[10], liteethmaccrc32inserter_reg[11], liteethmaccrc32inserter_reg[12], liteethmaccrc32inserter_reg[13], liteethmaccrc32inserter_reg[14], liteethmaccrc32inserter_reg[15], liteethmaccrc32inserter_reg[16], liteethmaccrc32inserter_reg[17], liteethmaccrc32inserter_reg[18], liteethmaccrc32inserter_reg[19], liteethmaccrc32inserter_reg[20], liteethmaccrc32inserter_reg[21], liteethmaccrc32inserter_reg[22], liteethmaccrc32inserter_reg[23], liteethmaccrc32inserter_reg[24], liteethmaccrc32inserter_reg[25], liteethmaccrc32inserter_reg[26], liteethmaccrc32inserter_reg[27], liteethmaccrc32inserter_reg[28], liteethmaccrc32inserter_reg[29], liteethmaccrc32inserter_reg[30], liteethmaccrc32inserter_reg[31]});
|
|
assign liteethmaccrc32inserter_error = (liteethmaccrc32inserter_next != 32'd3338984827);
|
|
always @(*) begin
|
|
liteethmaccrc32inserter_next <= 32'd0;
|
|
liteethmaccrc32inserter_next[0] <= (((liteethmaccrc32inserter_last[24] ^ liteethmaccrc32inserter_last[30]) ^ liteethmaccrc32inserter_data1[1]) ^ liteethmaccrc32inserter_data1[7]);
|
|
liteethmaccrc32inserter_next[1] <= (((((((liteethmaccrc32inserter_last[25] ^ liteethmaccrc32inserter_last[31]) ^ liteethmaccrc32inserter_data1[0]) ^ liteethmaccrc32inserter_data1[6]) ^ liteethmaccrc32inserter_last[24]) ^ liteethmaccrc32inserter_last[30]) ^ liteethmaccrc32inserter_data1[1]) ^ liteethmaccrc32inserter_data1[7]);
|
|
liteethmaccrc32inserter_next[2] <= (((((((((liteethmaccrc32inserter_last[26] ^ liteethmaccrc32inserter_data1[5]) ^ liteethmaccrc32inserter_last[25]) ^ liteethmaccrc32inserter_last[31]) ^ liteethmaccrc32inserter_data1[0]) ^ liteethmaccrc32inserter_data1[6]) ^ liteethmaccrc32inserter_last[24]) ^ liteethmaccrc32inserter_last[30]) ^ liteethmaccrc32inserter_data1[1]) ^ liteethmaccrc32inserter_data1[7]);
|
|
liteethmaccrc32inserter_next[3] <= (((((((liteethmaccrc32inserter_last[27] ^ liteethmaccrc32inserter_data1[4]) ^ liteethmaccrc32inserter_last[26]) ^ liteethmaccrc32inserter_data1[5]) ^ liteethmaccrc32inserter_last[25]) ^ liteethmaccrc32inserter_last[31]) ^ liteethmaccrc32inserter_data1[0]) ^ liteethmaccrc32inserter_data1[6]);
|
|
liteethmaccrc32inserter_next[4] <= (((((((((liteethmaccrc32inserter_last[28] ^ liteethmaccrc32inserter_data1[3]) ^ liteethmaccrc32inserter_last[27]) ^ liteethmaccrc32inserter_data1[4]) ^ liteethmaccrc32inserter_last[26]) ^ liteethmaccrc32inserter_data1[5]) ^ liteethmaccrc32inserter_last[24]) ^ liteethmaccrc32inserter_last[30]) ^ liteethmaccrc32inserter_data1[1]) ^ liteethmaccrc32inserter_data1[7]);
|
|
liteethmaccrc32inserter_next[5] <= (((((((((((((liteethmaccrc32inserter_last[29] ^ liteethmaccrc32inserter_data1[2]) ^ liteethmaccrc32inserter_last[28]) ^ liteethmaccrc32inserter_data1[3]) ^ liteethmaccrc32inserter_last[27]) ^ liteethmaccrc32inserter_data1[4]) ^ liteethmaccrc32inserter_last[25]) ^ liteethmaccrc32inserter_last[31]) ^ liteethmaccrc32inserter_data1[0]) ^ liteethmaccrc32inserter_data1[6]) ^ liteethmaccrc32inserter_last[24]) ^ liteethmaccrc32inserter_last[30]) ^ liteethmaccrc32inserter_data1[1]) ^ liteethmaccrc32inserter_data1[7]);
|
|
liteethmaccrc32inserter_next[6] <= (((((((((((liteethmaccrc32inserter_last[30] ^ liteethmaccrc32inserter_data1[1]) ^ liteethmaccrc32inserter_last[29]) ^ liteethmaccrc32inserter_data1[2]) ^ liteethmaccrc32inserter_last[28]) ^ liteethmaccrc32inserter_data1[3]) ^ liteethmaccrc32inserter_last[26]) ^ liteethmaccrc32inserter_data1[5]) ^ liteethmaccrc32inserter_last[25]) ^ liteethmaccrc32inserter_last[31]) ^ liteethmaccrc32inserter_data1[0]) ^ liteethmaccrc32inserter_data1[6]);
|
|
liteethmaccrc32inserter_next[7] <= (((((((((liteethmaccrc32inserter_last[31] ^ liteethmaccrc32inserter_data1[0]) ^ liteethmaccrc32inserter_last[29]) ^ liteethmaccrc32inserter_data1[2]) ^ liteethmaccrc32inserter_last[27]) ^ liteethmaccrc32inserter_data1[4]) ^ liteethmaccrc32inserter_last[26]) ^ liteethmaccrc32inserter_data1[5]) ^ liteethmaccrc32inserter_last[24]) ^ liteethmaccrc32inserter_data1[7]);
|
|
liteethmaccrc32inserter_next[8] <= ((((((((liteethmaccrc32inserter_last[0] ^ liteethmaccrc32inserter_last[28]) ^ liteethmaccrc32inserter_data1[3]) ^ liteethmaccrc32inserter_last[27]) ^ liteethmaccrc32inserter_data1[4]) ^ liteethmaccrc32inserter_last[25]) ^ liteethmaccrc32inserter_data1[6]) ^ liteethmaccrc32inserter_last[24]) ^ liteethmaccrc32inserter_data1[7]);
|
|
liteethmaccrc32inserter_next[9] <= ((((((((liteethmaccrc32inserter_last[1] ^ liteethmaccrc32inserter_last[29]) ^ liteethmaccrc32inserter_data1[2]) ^ liteethmaccrc32inserter_last[28]) ^ liteethmaccrc32inserter_data1[3]) ^ liteethmaccrc32inserter_last[26]) ^ liteethmaccrc32inserter_data1[5]) ^ liteethmaccrc32inserter_last[25]) ^ liteethmaccrc32inserter_data1[6]);
|
|
liteethmaccrc32inserter_next[10] <= ((((((((liteethmaccrc32inserter_last[2] ^ liteethmaccrc32inserter_last[29]) ^ liteethmaccrc32inserter_data1[2]) ^ liteethmaccrc32inserter_last[27]) ^ liteethmaccrc32inserter_data1[4]) ^ liteethmaccrc32inserter_last[26]) ^ liteethmaccrc32inserter_data1[5]) ^ liteethmaccrc32inserter_last[24]) ^ liteethmaccrc32inserter_data1[7]);
|
|
liteethmaccrc32inserter_next[11] <= ((((((((liteethmaccrc32inserter_last[3] ^ liteethmaccrc32inserter_last[28]) ^ liteethmaccrc32inserter_data1[3]) ^ liteethmaccrc32inserter_last[27]) ^ liteethmaccrc32inserter_data1[4]) ^ liteethmaccrc32inserter_last[25]) ^ liteethmaccrc32inserter_data1[6]) ^ liteethmaccrc32inserter_last[24]) ^ liteethmaccrc32inserter_data1[7]);
|
|
liteethmaccrc32inserter_next[12] <= ((((((((((((liteethmaccrc32inserter_last[4] ^ liteethmaccrc32inserter_last[29]) ^ liteethmaccrc32inserter_data1[2]) ^ liteethmaccrc32inserter_last[28]) ^ liteethmaccrc32inserter_data1[3]) ^ liteethmaccrc32inserter_last[26]) ^ liteethmaccrc32inserter_data1[5]) ^ liteethmaccrc32inserter_last[25]) ^ liteethmaccrc32inserter_data1[6]) ^ liteethmaccrc32inserter_last[24]) ^ liteethmaccrc32inserter_last[30]) ^ liteethmaccrc32inserter_data1[1]) ^ liteethmaccrc32inserter_data1[7]);
|
|
liteethmaccrc32inserter_next[13] <= ((((((((((((liteethmaccrc32inserter_last[5] ^ liteethmaccrc32inserter_last[30]) ^ liteethmaccrc32inserter_data1[1]) ^ liteethmaccrc32inserter_last[29]) ^ liteethmaccrc32inserter_data1[2]) ^ liteethmaccrc32inserter_last[27]) ^ liteethmaccrc32inserter_data1[4]) ^ liteethmaccrc32inserter_last[26]) ^ liteethmaccrc32inserter_data1[5]) ^ liteethmaccrc32inserter_last[25]) ^ liteethmaccrc32inserter_last[31]) ^ liteethmaccrc32inserter_data1[0]) ^ liteethmaccrc32inserter_data1[6]);
|
|
liteethmaccrc32inserter_next[14] <= ((((((((((liteethmaccrc32inserter_last[6] ^ liteethmaccrc32inserter_last[31]) ^ liteethmaccrc32inserter_data1[0]) ^ liteethmaccrc32inserter_last[30]) ^ liteethmaccrc32inserter_data1[1]) ^ liteethmaccrc32inserter_last[28]) ^ liteethmaccrc32inserter_data1[3]) ^ liteethmaccrc32inserter_last[27]) ^ liteethmaccrc32inserter_data1[4]) ^ liteethmaccrc32inserter_last[26]) ^ liteethmaccrc32inserter_data1[5]);
|
|
liteethmaccrc32inserter_next[15] <= ((((((((liteethmaccrc32inserter_last[7] ^ liteethmaccrc32inserter_last[31]) ^ liteethmaccrc32inserter_data1[0]) ^ liteethmaccrc32inserter_last[29]) ^ liteethmaccrc32inserter_data1[2]) ^ liteethmaccrc32inserter_last[28]) ^ liteethmaccrc32inserter_data1[3]) ^ liteethmaccrc32inserter_last[27]) ^ liteethmaccrc32inserter_data1[4]);
|
|
liteethmaccrc32inserter_next[16] <= ((((((liteethmaccrc32inserter_last[8] ^ liteethmaccrc32inserter_last[29]) ^ liteethmaccrc32inserter_data1[2]) ^ liteethmaccrc32inserter_last[28]) ^ liteethmaccrc32inserter_data1[3]) ^ liteethmaccrc32inserter_last[24]) ^ liteethmaccrc32inserter_data1[7]);
|
|
liteethmaccrc32inserter_next[17] <= ((((((liteethmaccrc32inserter_last[9] ^ liteethmaccrc32inserter_last[30]) ^ liteethmaccrc32inserter_data1[1]) ^ liteethmaccrc32inserter_last[29]) ^ liteethmaccrc32inserter_data1[2]) ^ liteethmaccrc32inserter_last[25]) ^ liteethmaccrc32inserter_data1[6]);
|
|
liteethmaccrc32inserter_next[18] <= ((((((liteethmaccrc32inserter_last[10] ^ liteethmaccrc32inserter_last[31]) ^ liteethmaccrc32inserter_data1[0]) ^ liteethmaccrc32inserter_last[30]) ^ liteethmaccrc32inserter_data1[1]) ^ liteethmaccrc32inserter_last[26]) ^ liteethmaccrc32inserter_data1[5]);
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liteethmaccrc32inserter_next[19] <= ((((liteethmaccrc32inserter_last[11] ^ liteethmaccrc32inserter_last[31]) ^ liteethmaccrc32inserter_data1[0]) ^ liteethmaccrc32inserter_last[27]) ^ liteethmaccrc32inserter_data1[4]);
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liteethmaccrc32inserter_next[20] <= ((liteethmaccrc32inserter_last[12] ^ liteethmaccrc32inserter_last[28]) ^ liteethmaccrc32inserter_data1[3]);
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liteethmaccrc32inserter_next[21] <= ((liteethmaccrc32inserter_last[13] ^ liteethmaccrc32inserter_last[29]) ^ liteethmaccrc32inserter_data1[2]);
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liteethmaccrc32inserter_next[22] <= ((liteethmaccrc32inserter_last[14] ^ liteethmaccrc32inserter_last[24]) ^ liteethmaccrc32inserter_data1[7]);
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liteethmaccrc32inserter_next[23] <= ((((((liteethmaccrc32inserter_last[15] ^ liteethmaccrc32inserter_last[25]) ^ liteethmaccrc32inserter_data1[6]) ^ liteethmaccrc32inserter_last[24]) ^ liteethmaccrc32inserter_last[30]) ^ liteethmaccrc32inserter_data1[1]) ^ liteethmaccrc32inserter_data1[7]);
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liteethmaccrc32inserter_next[24] <= ((((((liteethmaccrc32inserter_last[16] ^ liteethmaccrc32inserter_last[26]) ^ liteethmaccrc32inserter_data1[5]) ^ liteethmaccrc32inserter_last[25]) ^ liteethmaccrc32inserter_last[31]) ^ liteethmaccrc32inserter_data1[0]) ^ liteethmaccrc32inserter_data1[6]);
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liteethmaccrc32inserter_next[25] <= ((((liteethmaccrc32inserter_last[17] ^ liteethmaccrc32inserter_last[27]) ^ liteethmaccrc32inserter_data1[4]) ^ liteethmaccrc32inserter_last[26]) ^ liteethmaccrc32inserter_data1[5]);
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liteethmaccrc32inserter_next[26] <= ((((((((liteethmaccrc32inserter_last[18] ^ liteethmaccrc32inserter_last[28]) ^ liteethmaccrc32inserter_data1[3]) ^ liteethmaccrc32inserter_last[27]) ^ liteethmaccrc32inserter_data1[4]) ^ liteethmaccrc32inserter_last[24]) ^ liteethmaccrc32inserter_last[30]) ^ liteethmaccrc32inserter_data1[1]) ^ liteethmaccrc32inserter_data1[7]);
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liteethmaccrc32inserter_next[27] <= ((((((((liteethmaccrc32inserter_last[19] ^ liteethmaccrc32inserter_last[29]) ^ liteethmaccrc32inserter_data1[2]) ^ liteethmaccrc32inserter_last[28]) ^ liteethmaccrc32inserter_data1[3]) ^ liteethmaccrc32inserter_last[25]) ^ liteethmaccrc32inserter_last[31]) ^ liteethmaccrc32inserter_data1[0]) ^ liteethmaccrc32inserter_data1[6]);
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liteethmaccrc32inserter_next[28] <= ((((((liteethmaccrc32inserter_last[20] ^ liteethmaccrc32inserter_last[30]) ^ liteethmaccrc32inserter_data1[1]) ^ liteethmaccrc32inserter_last[29]) ^ liteethmaccrc32inserter_data1[2]) ^ liteethmaccrc32inserter_last[26]) ^ liteethmaccrc32inserter_data1[5]);
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liteethmaccrc32inserter_next[29] <= ((((((liteethmaccrc32inserter_last[21] ^ liteethmaccrc32inserter_last[31]) ^ liteethmaccrc32inserter_data1[0]) ^ liteethmaccrc32inserter_last[30]) ^ liteethmaccrc32inserter_data1[1]) ^ liteethmaccrc32inserter_last[27]) ^ liteethmaccrc32inserter_data1[4]);
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liteethmaccrc32inserter_next[30] <= ((((liteethmaccrc32inserter_last[22] ^ liteethmaccrc32inserter_last[31]) ^ liteethmaccrc32inserter_data1[0]) ^ liteethmaccrc32inserter_last[28]) ^ liteethmaccrc32inserter_data1[3]);
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liteethmaccrc32inserter_next[31] <= ((liteethmaccrc32inserter_last[23] ^ liteethmaccrc32inserter_last[29]) ^ liteethmaccrc32inserter_data1[2]);
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end
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always @(*) begin
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liteethmaccrc32inserter_source_first <= 1'd0;
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liteethmaccrc32inserter_source_last <= 1'd0;
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liteethmaccrc32inserter_source_payload_data <= 8'd0;
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liteethmaccrc32inserter_source_payload_last_be <= 1'd0;
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liteethmaccrc32inserter_source_payload_error <= 1'd0;
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liteethmaccrc32inserter_data0 <= 8'd0;
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liteethmaccrc32inserter_is_ongoing0 <= 1'd0;
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liteethmaccrc32inserter_sink_ready <= 1'd0;
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liteethmaccrc32inserter_is_ongoing1 <= 1'd0;
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liteethmaccrc32inserter_ce <= 1'd0;
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liteethmaccrc32inserter_reset <= 1'd0;
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subfragments_liteethmaccrc32inserter_next_state <= 2'd0;
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liteethmaccrc32inserter_source_valid <= 1'd0;
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subfragments_liteethmaccrc32inserter_next_state <= subfragments_liteethmaccrc32inserter_state;
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case (subfragments_liteethmaccrc32inserter_state)
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1'd1: begin
|
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liteethmaccrc32inserter_ce <= (liteethmaccrc32inserter_sink_valid & liteethmaccrc32inserter_source_ready);
|
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liteethmaccrc32inserter_data0 <= liteethmaccrc32inserter_sink_payload_data;
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liteethmaccrc32inserter_source_valid <= liteethmaccrc32inserter_sink_valid;
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liteethmaccrc32inserter_sink_ready <= liteethmaccrc32inserter_source_ready;
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liteethmaccrc32inserter_source_first <= liteethmaccrc32inserter_sink_first;
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|
liteethmaccrc32inserter_source_last <= liteethmaccrc32inserter_sink_last;
|
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liteethmaccrc32inserter_source_payload_data <= liteethmaccrc32inserter_sink_payload_data;
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liteethmaccrc32inserter_source_payload_last_be <= liteethmaccrc32inserter_sink_payload_last_be;
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liteethmaccrc32inserter_source_payload_error <= liteethmaccrc32inserter_sink_payload_error;
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|
liteethmaccrc32inserter_source_last <= 1'd0;
|
|
if (((liteethmaccrc32inserter_sink_valid & liteethmaccrc32inserter_sink_last) & liteethmaccrc32inserter_source_ready)) begin
|
|
subfragments_liteethmaccrc32inserter_next_state <= 2'd2;
|
|
end
|
|
end
|
|
2'd2: begin
|
|
liteethmaccrc32inserter_source_valid <= 1'd1;
|
|
case (liteethmaccrc32inserter_cnt)
|
|
1'd0: begin
|
|
liteethmaccrc32inserter_source_payload_data <= liteethmaccrc32inserter_value[31:24];
|
|
end
|
|
1'd1: begin
|
|
liteethmaccrc32inserter_source_payload_data <= liteethmaccrc32inserter_value[23:16];
|
|
end
|
|
2'd2: begin
|
|
liteethmaccrc32inserter_source_payload_data <= liteethmaccrc32inserter_value[15:8];
|
|
end
|
|
default: begin
|
|
liteethmaccrc32inserter_source_payload_data <= liteethmaccrc32inserter_value[7:0];
|
|
end
|
|
endcase
|
|
if (liteethmaccrc32inserter_cnt_done) begin
|
|
liteethmaccrc32inserter_source_last <= 1'd1;
|
|
if (liteethmaccrc32inserter_source_ready) begin
|
|
subfragments_liteethmaccrc32inserter_next_state <= 1'd0;
|
|
end
|
|
end
|
|
liteethmaccrc32inserter_is_ongoing1 <= 1'd1;
|
|
end
|
|
default: begin
|
|
liteethmaccrc32inserter_reset <= 1'd1;
|
|
liteethmaccrc32inserter_sink_ready <= 1'd1;
|
|
if (liteethmaccrc32inserter_sink_valid) begin
|
|
liteethmaccrc32inserter_sink_ready <= 1'd0;
|
|
subfragments_liteethmaccrc32inserter_next_state <= 1'd1;
|
|
end
|
|
liteethmaccrc32inserter_is_ongoing0 <= 1'd1;
|
|
end
|
|
endcase
|
|
end
|
|
assign crc32_inserter_sink_ready = ((~crc32_inserter_source_valid) | crc32_inserter_source_ready);
|
|
assign liteethmaccrc32checker_fifo_full = (liteethmaccrc32checker_syncfifo_level == 3'd4);
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|
assign liteethmaccrc32checker_fifo_in = (liteethmaccrc32checker_sink_sink_valid & ((~liteethmaccrc32checker_fifo_full) | liteethmaccrc32checker_fifo_out));
|
|
assign liteethmaccrc32checker_fifo_out = (liteethmaccrc32checker_source_source_valid & liteethmaccrc32checker_source_source_ready);
|
|
assign liteethmaccrc32checker_syncfifo_sink_first = liteethmaccrc32checker_sink_sink_first;
|
|
assign liteethmaccrc32checker_syncfifo_sink_last = liteethmaccrc32checker_sink_sink_last;
|
|
assign liteethmaccrc32checker_syncfifo_sink_payload_data = liteethmaccrc32checker_sink_sink_payload_data;
|
|
assign liteethmaccrc32checker_syncfifo_sink_payload_last_be = liteethmaccrc32checker_sink_sink_payload_last_be;
|
|
assign liteethmaccrc32checker_syncfifo_sink_payload_error = liteethmaccrc32checker_sink_sink_payload_error;
|
|
always @(*) begin
|
|
liteethmaccrc32checker_syncfifo_sink_valid <= 1'd0;
|
|
liteethmaccrc32checker_syncfifo_sink_valid <= liteethmaccrc32checker_sink_sink_valid;
|
|
liteethmaccrc32checker_syncfifo_sink_valid <= liteethmaccrc32checker_fifo_in;
|
|
end
|
|
always @(*) begin
|
|
liteethmaccrc32checker_sink_sink_ready <= 1'd0;
|
|
liteethmaccrc32checker_sink_sink_ready <= liteethmaccrc32checker_syncfifo_sink_ready;
|
|
liteethmaccrc32checker_sink_sink_ready <= liteethmaccrc32checker_fifo_in;
|
|
end
|
|
assign liteethmaccrc32checker_source_source_valid = (liteethmaccrc32checker_sink_sink_valid & liteethmaccrc32checker_fifo_full);
|
|
assign liteethmaccrc32checker_source_source_last = liteethmaccrc32checker_sink_sink_last;
|
|
assign liteethmaccrc32checker_syncfifo_source_ready = liteethmaccrc32checker_fifo_out;
|
|
assign liteethmaccrc32checker_source_source_payload_data = liteethmaccrc32checker_syncfifo_source_payload_data;
|
|
assign liteethmaccrc32checker_source_source_payload_last_be = liteethmaccrc32checker_syncfifo_source_payload_last_be;
|
|
always @(*) begin
|
|
liteethmaccrc32checker_source_source_payload_error <= 1'd0;
|
|
liteethmaccrc32checker_source_source_payload_error <= liteethmaccrc32checker_syncfifo_source_payload_error;
|
|
liteethmaccrc32checker_source_source_payload_error <= (liteethmaccrc32checker_sink_sink_payload_error | liteethmaccrc32checker_crc_error);
|
|
end
|
|
assign liteethmaccrc32checker_error = ((liteethmaccrc32checker_source_source_valid & liteethmaccrc32checker_source_source_last) & liteethmaccrc32checker_crc_error);
|
|
assign liteethmaccrc32checker_crc_data0 = liteethmaccrc32checker_sink_sink_payload_data;
|
|
assign liteethmaccrc32checker_sink_sink_valid = crc32_checker_source_valid;
|
|
assign crc32_checker_source_ready = liteethmaccrc32checker_sink_sink_ready;
|
|
assign liteethmaccrc32checker_sink_sink_first = crc32_checker_source_first;
|
|
assign liteethmaccrc32checker_sink_sink_last = crc32_checker_source_last;
|
|
assign liteethmaccrc32checker_sink_sink_payload_data = crc32_checker_source_payload_data;
|
|
assign liteethmaccrc32checker_sink_sink_payload_last_be = crc32_checker_source_payload_last_be;
|
|
assign liteethmaccrc32checker_sink_sink_payload_error = crc32_checker_source_payload_error;
|
|
assign liteethmaccrc32checker_crc_data1 = liteethmaccrc32checker_crc_data0;
|
|
assign liteethmaccrc32checker_crc_last = liteethmaccrc32checker_crc_reg;
|
|
assign liteethmaccrc32checker_crc_value = (~{liteethmaccrc32checker_crc_reg[0], liteethmaccrc32checker_crc_reg[1], liteethmaccrc32checker_crc_reg[2], liteethmaccrc32checker_crc_reg[3], liteethmaccrc32checker_crc_reg[4], liteethmaccrc32checker_crc_reg[5], liteethmaccrc32checker_crc_reg[6], liteethmaccrc32checker_crc_reg[7], liteethmaccrc32checker_crc_reg[8], liteethmaccrc32checker_crc_reg[9], liteethmaccrc32checker_crc_reg[10], liteethmaccrc32checker_crc_reg[11], liteethmaccrc32checker_crc_reg[12], liteethmaccrc32checker_crc_reg[13], liteethmaccrc32checker_crc_reg[14], liteethmaccrc32checker_crc_reg[15], liteethmaccrc32checker_crc_reg[16], liteethmaccrc32checker_crc_reg[17], liteethmaccrc32checker_crc_reg[18], liteethmaccrc32checker_crc_reg[19], liteethmaccrc32checker_crc_reg[20], liteethmaccrc32checker_crc_reg[21], liteethmaccrc32checker_crc_reg[22], liteethmaccrc32checker_crc_reg[23], liteethmaccrc32checker_crc_reg[24], liteethmaccrc32checker_crc_reg[25], liteethmaccrc32checker_crc_reg[26], liteethmaccrc32checker_crc_reg[27], liteethmaccrc32checker_crc_reg[28], liteethmaccrc32checker_crc_reg[29], liteethmaccrc32checker_crc_reg[30], liteethmaccrc32checker_crc_reg[31]});
|
|
assign liteethmaccrc32checker_crc_error = (liteethmaccrc32checker_crc_next != 32'd3338984827);
|
|
always @(*) begin
|
|
liteethmaccrc32checker_crc_next <= 32'd0;
|
|
liteethmaccrc32checker_crc_next[0] <= (((liteethmaccrc32checker_crc_last[24] ^ liteethmaccrc32checker_crc_last[30]) ^ liteethmaccrc32checker_crc_data1[1]) ^ liteethmaccrc32checker_crc_data1[7]);
|
|
liteethmaccrc32checker_crc_next[1] <= (((((((liteethmaccrc32checker_crc_last[25] ^ liteethmaccrc32checker_crc_last[31]) ^ liteethmaccrc32checker_crc_data1[0]) ^ liteethmaccrc32checker_crc_data1[6]) ^ liteethmaccrc32checker_crc_last[24]) ^ liteethmaccrc32checker_crc_last[30]) ^ liteethmaccrc32checker_crc_data1[1]) ^ liteethmaccrc32checker_crc_data1[7]);
|
|
liteethmaccrc32checker_crc_next[2] <= (((((((((liteethmaccrc32checker_crc_last[26] ^ liteethmaccrc32checker_crc_data1[5]) ^ liteethmaccrc32checker_crc_last[25]) ^ liteethmaccrc32checker_crc_last[31]) ^ liteethmaccrc32checker_crc_data1[0]) ^ liteethmaccrc32checker_crc_data1[6]) ^ liteethmaccrc32checker_crc_last[24]) ^ liteethmaccrc32checker_crc_last[30]) ^ liteethmaccrc32checker_crc_data1[1]) ^ liteethmaccrc32checker_crc_data1[7]);
|
|
liteethmaccrc32checker_crc_next[3] <= (((((((liteethmaccrc32checker_crc_last[27] ^ liteethmaccrc32checker_crc_data1[4]) ^ liteethmaccrc32checker_crc_last[26]) ^ liteethmaccrc32checker_crc_data1[5]) ^ liteethmaccrc32checker_crc_last[25]) ^ liteethmaccrc32checker_crc_last[31]) ^ liteethmaccrc32checker_crc_data1[0]) ^ liteethmaccrc32checker_crc_data1[6]);
|
|
liteethmaccrc32checker_crc_next[4] <= (((((((((liteethmaccrc32checker_crc_last[28] ^ liteethmaccrc32checker_crc_data1[3]) ^ liteethmaccrc32checker_crc_last[27]) ^ liteethmaccrc32checker_crc_data1[4]) ^ liteethmaccrc32checker_crc_last[26]) ^ liteethmaccrc32checker_crc_data1[5]) ^ liteethmaccrc32checker_crc_last[24]) ^ liteethmaccrc32checker_crc_last[30]) ^ liteethmaccrc32checker_crc_data1[1]) ^ liteethmaccrc32checker_crc_data1[7]);
|
|
liteethmaccrc32checker_crc_next[5] <= (((((((((((((liteethmaccrc32checker_crc_last[29] ^ liteethmaccrc32checker_crc_data1[2]) ^ liteethmaccrc32checker_crc_last[28]) ^ liteethmaccrc32checker_crc_data1[3]) ^ liteethmaccrc32checker_crc_last[27]) ^ liteethmaccrc32checker_crc_data1[4]) ^ liteethmaccrc32checker_crc_last[25]) ^ liteethmaccrc32checker_crc_last[31]) ^ liteethmaccrc32checker_crc_data1[0]) ^ liteethmaccrc32checker_crc_data1[6]) ^ liteethmaccrc32checker_crc_last[24]) ^ liteethmaccrc32checker_crc_last[30]) ^ liteethmaccrc32checker_crc_data1[1]) ^ liteethmaccrc32checker_crc_data1[7]);
|
|
liteethmaccrc32checker_crc_next[6] <= (((((((((((liteethmaccrc32checker_crc_last[30] ^ liteethmaccrc32checker_crc_data1[1]) ^ liteethmaccrc32checker_crc_last[29]) ^ liteethmaccrc32checker_crc_data1[2]) ^ liteethmaccrc32checker_crc_last[28]) ^ liteethmaccrc32checker_crc_data1[3]) ^ liteethmaccrc32checker_crc_last[26]) ^ liteethmaccrc32checker_crc_data1[5]) ^ liteethmaccrc32checker_crc_last[25]) ^ liteethmaccrc32checker_crc_last[31]) ^ liteethmaccrc32checker_crc_data1[0]) ^ liteethmaccrc32checker_crc_data1[6]);
|
|
liteethmaccrc32checker_crc_next[7] <= (((((((((liteethmaccrc32checker_crc_last[31] ^ liteethmaccrc32checker_crc_data1[0]) ^ liteethmaccrc32checker_crc_last[29]) ^ liteethmaccrc32checker_crc_data1[2]) ^ liteethmaccrc32checker_crc_last[27]) ^ liteethmaccrc32checker_crc_data1[4]) ^ liteethmaccrc32checker_crc_last[26]) ^ liteethmaccrc32checker_crc_data1[5]) ^ liteethmaccrc32checker_crc_last[24]) ^ liteethmaccrc32checker_crc_data1[7]);
|
|
liteethmaccrc32checker_crc_next[8] <= ((((((((liteethmaccrc32checker_crc_last[0] ^ liteethmaccrc32checker_crc_last[28]) ^ liteethmaccrc32checker_crc_data1[3]) ^ liteethmaccrc32checker_crc_last[27]) ^ liteethmaccrc32checker_crc_data1[4]) ^ liteethmaccrc32checker_crc_last[25]) ^ liteethmaccrc32checker_crc_data1[6]) ^ liteethmaccrc32checker_crc_last[24]) ^ liteethmaccrc32checker_crc_data1[7]);
|
|
liteethmaccrc32checker_crc_next[9] <= ((((((((liteethmaccrc32checker_crc_last[1] ^ liteethmaccrc32checker_crc_last[29]) ^ liteethmaccrc32checker_crc_data1[2]) ^ liteethmaccrc32checker_crc_last[28]) ^ liteethmaccrc32checker_crc_data1[3]) ^ liteethmaccrc32checker_crc_last[26]) ^ liteethmaccrc32checker_crc_data1[5]) ^ liteethmaccrc32checker_crc_last[25]) ^ liteethmaccrc32checker_crc_data1[6]);
|
|
liteethmaccrc32checker_crc_next[10] <= ((((((((liteethmaccrc32checker_crc_last[2] ^ liteethmaccrc32checker_crc_last[29]) ^ liteethmaccrc32checker_crc_data1[2]) ^ liteethmaccrc32checker_crc_last[27]) ^ liteethmaccrc32checker_crc_data1[4]) ^ liteethmaccrc32checker_crc_last[26]) ^ liteethmaccrc32checker_crc_data1[5]) ^ liteethmaccrc32checker_crc_last[24]) ^ liteethmaccrc32checker_crc_data1[7]);
|
|
liteethmaccrc32checker_crc_next[11] <= ((((((((liteethmaccrc32checker_crc_last[3] ^ liteethmaccrc32checker_crc_last[28]) ^ liteethmaccrc32checker_crc_data1[3]) ^ liteethmaccrc32checker_crc_last[27]) ^ liteethmaccrc32checker_crc_data1[4]) ^ liteethmaccrc32checker_crc_last[25]) ^ liteethmaccrc32checker_crc_data1[6]) ^ liteethmaccrc32checker_crc_last[24]) ^ liteethmaccrc32checker_crc_data1[7]);
|
|
liteethmaccrc32checker_crc_next[12] <= ((((((((((((liteethmaccrc32checker_crc_last[4] ^ liteethmaccrc32checker_crc_last[29]) ^ liteethmaccrc32checker_crc_data1[2]) ^ liteethmaccrc32checker_crc_last[28]) ^ liteethmaccrc32checker_crc_data1[3]) ^ liteethmaccrc32checker_crc_last[26]) ^ liteethmaccrc32checker_crc_data1[5]) ^ liteethmaccrc32checker_crc_last[25]) ^ liteethmaccrc32checker_crc_data1[6]) ^ liteethmaccrc32checker_crc_last[24]) ^ liteethmaccrc32checker_crc_last[30]) ^ liteethmaccrc32checker_crc_data1[1]) ^ liteethmaccrc32checker_crc_data1[7]);
|
|
liteethmaccrc32checker_crc_next[13] <= ((((((((((((liteethmaccrc32checker_crc_last[5] ^ liteethmaccrc32checker_crc_last[30]) ^ liteethmaccrc32checker_crc_data1[1]) ^ liteethmaccrc32checker_crc_last[29]) ^ liteethmaccrc32checker_crc_data1[2]) ^ liteethmaccrc32checker_crc_last[27]) ^ liteethmaccrc32checker_crc_data1[4]) ^ liteethmaccrc32checker_crc_last[26]) ^ liteethmaccrc32checker_crc_data1[5]) ^ liteethmaccrc32checker_crc_last[25]) ^ liteethmaccrc32checker_crc_last[31]) ^ liteethmaccrc32checker_crc_data1[0]) ^ liteethmaccrc32checker_crc_data1[6]);
|
|
liteethmaccrc32checker_crc_next[14] <= ((((((((((liteethmaccrc32checker_crc_last[6] ^ liteethmaccrc32checker_crc_last[31]) ^ liteethmaccrc32checker_crc_data1[0]) ^ liteethmaccrc32checker_crc_last[30]) ^ liteethmaccrc32checker_crc_data1[1]) ^ liteethmaccrc32checker_crc_last[28]) ^ liteethmaccrc32checker_crc_data1[3]) ^ liteethmaccrc32checker_crc_last[27]) ^ liteethmaccrc32checker_crc_data1[4]) ^ liteethmaccrc32checker_crc_last[26]) ^ liteethmaccrc32checker_crc_data1[5]);
|
|
liteethmaccrc32checker_crc_next[15] <= ((((((((liteethmaccrc32checker_crc_last[7] ^ liteethmaccrc32checker_crc_last[31]) ^ liteethmaccrc32checker_crc_data1[0]) ^ liteethmaccrc32checker_crc_last[29]) ^ liteethmaccrc32checker_crc_data1[2]) ^ liteethmaccrc32checker_crc_last[28]) ^ liteethmaccrc32checker_crc_data1[3]) ^ liteethmaccrc32checker_crc_last[27]) ^ liteethmaccrc32checker_crc_data1[4]);
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|
liteethmaccrc32checker_crc_next[16] <= ((((((liteethmaccrc32checker_crc_last[8] ^ liteethmaccrc32checker_crc_last[29]) ^ liteethmaccrc32checker_crc_data1[2]) ^ liteethmaccrc32checker_crc_last[28]) ^ liteethmaccrc32checker_crc_data1[3]) ^ liteethmaccrc32checker_crc_last[24]) ^ liteethmaccrc32checker_crc_data1[7]);
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|
liteethmaccrc32checker_crc_next[17] <= ((((((liteethmaccrc32checker_crc_last[9] ^ liteethmaccrc32checker_crc_last[30]) ^ liteethmaccrc32checker_crc_data1[1]) ^ liteethmaccrc32checker_crc_last[29]) ^ liteethmaccrc32checker_crc_data1[2]) ^ liteethmaccrc32checker_crc_last[25]) ^ liteethmaccrc32checker_crc_data1[6]);
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|
liteethmaccrc32checker_crc_next[18] <= ((((((liteethmaccrc32checker_crc_last[10] ^ liteethmaccrc32checker_crc_last[31]) ^ liteethmaccrc32checker_crc_data1[0]) ^ liteethmaccrc32checker_crc_last[30]) ^ liteethmaccrc32checker_crc_data1[1]) ^ liteethmaccrc32checker_crc_last[26]) ^ liteethmaccrc32checker_crc_data1[5]);
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|
liteethmaccrc32checker_crc_next[19] <= ((((liteethmaccrc32checker_crc_last[11] ^ liteethmaccrc32checker_crc_last[31]) ^ liteethmaccrc32checker_crc_data1[0]) ^ liteethmaccrc32checker_crc_last[27]) ^ liteethmaccrc32checker_crc_data1[4]);
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|
liteethmaccrc32checker_crc_next[20] <= ((liteethmaccrc32checker_crc_last[12] ^ liteethmaccrc32checker_crc_last[28]) ^ liteethmaccrc32checker_crc_data1[3]);
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|
liteethmaccrc32checker_crc_next[21] <= ((liteethmaccrc32checker_crc_last[13] ^ liteethmaccrc32checker_crc_last[29]) ^ liteethmaccrc32checker_crc_data1[2]);
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|
liteethmaccrc32checker_crc_next[22] <= ((liteethmaccrc32checker_crc_last[14] ^ liteethmaccrc32checker_crc_last[24]) ^ liteethmaccrc32checker_crc_data1[7]);
|
|
liteethmaccrc32checker_crc_next[23] <= ((((((liteethmaccrc32checker_crc_last[15] ^ liteethmaccrc32checker_crc_last[25]) ^ liteethmaccrc32checker_crc_data1[6]) ^ liteethmaccrc32checker_crc_last[24]) ^ liteethmaccrc32checker_crc_last[30]) ^ liteethmaccrc32checker_crc_data1[1]) ^ liteethmaccrc32checker_crc_data1[7]);
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|
liteethmaccrc32checker_crc_next[24] <= ((((((liteethmaccrc32checker_crc_last[16] ^ liteethmaccrc32checker_crc_last[26]) ^ liteethmaccrc32checker_crc_data1[5]) ^ liteethmaccrc32checker_crc_last[25]) ^ liteethmaccrc32checker_crc_last[31]) ^ liteethmaccrc32checker_crc_data1[0]) ^ liteethmaccrc32checker_crc_data1[6]);
|
|
liteethmaccrc32checker_crc_next[25] <= ((((liteethmaccrc32checker_crc_last[17] ^ liteethmaccrc32checker_crc_last[27]) ^ liteethmaccrc32checker_crc_data1[4]) ^ liteethmaccrc32checker_crc_last[26]) ^ liteethmaccrc32checker_crc_data1[5]);
|
|
liteethmaccrc32checker_crc_next[26] <= ((((((((liteethmaccrc32checker_crc_last[18] ^ liteethmaccrc32checker_crc_last[28]) ^ liteethmaccrc32checker_crc_data1[3]) ^ liteethmaccrc32checker_crc_last[27]) ^ liteethmaccrc32checker_crc_data1[4]) ^ liteethmaccrc32checker_crc_last[24]) ^ liteethmaccrc32checker_crc_last[30]) ^ liteethmaccrc32checker_crc_data1[1]) ^ liteethmaccrc32checker_crc_data1[7]);
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|
liteethmaccrc32checker_crc_next[27] <= ((((((((liteethmaccrc32checker_crc_last[19] ^ liteethmaccrc32checker_crc_last[29]) ^ liteethmaccrc32checker_crc_data1[2]) ^ liteethmaccrc32checker_crc_last[28]) ^ liteethmaccrc32checker_crc_data1[3]) ^ liteethmaccrc32checker_crc_last[25]) ^ liteethmaccrc32checker_crc_last[31]) ^ liteethmaccrc32checker_crc_data1[0]) ^ liteethmaccrc32checker_crc_data1[6]);
|
|
liteethmaccrc32checker_crc_next[28] <= ((((((liteethmaccrc32checker_crc_last[20] ^ liteethmaccrc32checker_crc_last[30]) ^ liteethmaccrc32checker_crc_data1[1]) ^ liteethmaccrc32checker_crc_last[29]) ^ liteethmaccrc32checker_crc_data1[2]) ^ liteethmaccrc32checker_crc_last[26]) ^ liteethmaccrc32checker_crc_data1[5]);
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|
liteethmaccrc32checker_crc_next[29] <= ((((((liteethmaccrc32checker_crc_last[21] ^ liteethmaccrc32checker_crc_last[31]) ^ liteethmaccrc32checker_crc_data1[0]) ^ liteethmaccrc32checker_crc_last[30]) ^ liteethmaccrc32checker_crc_data1[1]) ^ liteethmaccrc32checker_crc_last[27]) ^ liteethmaccrc32checker_crc_data1[4]);
|
|
liteethmaccrc32checker_crc_next[30] <= ((((liteethmaccrc32checker_crc_last[22] ^ liteethmaccrc32checker_crc_last[31]) ^ liteethmaccrc32checker_crc_data1[0]) ^ liteethmaccrc32checker_crc_last[28]) ^ liteethmaccrc32checker_crc_data1[3]);
|
|
liteethmaccrc32checker_crc_next[31] <= ((liteethmaccrc32checker_crc_last[23] ^ liteethmaccrc32checker_crc_last[29]) ^ liteethmaccrc32checker_crc_data1[2]);
|
|
end
|
|
assign liteethmaccrc32checker_syncfifo_syncfifo_din = {liteethmaccrc32checker_syncfifo_fifo_in_last, liteethmaccrc32checker_syncfifo_fifo_in_first, liteethmaccrc32checker_syncfifo_fifo_in_payload_error, liteethmaccrc32checker_syncfifo_fifo_in_payload_last_be, liteethmaccrc32checker_syncfifo_fifo_in_payload_data};
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assign {liteethmaccrc32checker_syncfifo_fifo_out_last, liteethmaccrc32checker_syncfifo_fifo_out_first, liteethmaccrc32checker_syncfifo_fifo_out_payload_error, liteethmaccrc32checker_syncfifo_fifo_out_payload_last_be, liteethmaccrc32checker_syncfifo_fifo_out_payload_data} = liteethmaccrc32checker_syncfifo_syncfifo_dout;
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assign liteethmaccrc32checker_syncfifo_sink_ready = liteethmaccrc32checker_syncfifo_syncfifo_writable;
|
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assign liteethmaccrc32checker_syncfifo_syncfifo_we = liteethmaccrc32checker_syncfifo_sink_valid;
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assign liteethmaccrc32checker_syncfifo_fifo_in_first = liteethmaccrc32checker_syncfifo_sink_first;
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assign liteethmaccrc32checker_syncfifo_fifo_in_last = liteethmaccrc32checker_syncfifo_sink_last;
|
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assign liteethmaccrc32checker_syncfifo_fifo_in_payload_data = liteethmaccrc32checker_syncfifo_sink_payload_data;
|
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assign liteethmaccrc32checker_syncfifo_fifo_in_payload_last_be = liteethmaccrc32checker_syncfifo_sink_payload_last_be;
|
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assign liteethmaccrc32checker_syncfifo_fifo_in_payload_error = liteethmaccrc32checker_syncfifo_sink_payload_error;
|
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assign liteethmaccrc32checker_syncfifo_source_valid = liteethmaccrc32checker_syncfifo_syncfifo_readable;
|
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assign liteethmaccrc32checker_syncfifo_source_first = liteethmaccrc32checker_syncfifo_fifo_out_first;
|
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assign liteethmaccrc32checker_syncfifo_source_last = liteethmaccrc32checker_syncfifo_fifo_out_last;
|
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assign liteethmaccrc32checker_syncfifo_source_payload_data = liteethmaccrc32checker_syncfifo_fifo_out_payload_data;
|
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assign liteethmaccrc32checker_syncfifo_source_payload_last_be = liteethmaccrc32checker_syncfifo_fifo_out_payload_last_be;
|
|
assign liteethmaccrc32checker_syncfifo_source_payload_error = liteethmaccrc32checker_syncfifo_fifo_out_payload_error;
|
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assign liteethmaccrc32checker_syncfifo_syncfifo_re = liteethmaccrc32checker_syncfifo_source_ready;
|
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always @(*) begin
|
|
liteethmaccrc32checker_syncfifo_wrport_adr <= 3'd0;
|
|
if (liteethmaccrc32checker_syncfifo_replace) begin
|
|
liteethmaccrc32checker_syncfifo_wrport_adr <= (liteethmaccrc32checker_syncfifo_produce - 1'd1);
|
|
end else begin
|
|
liteethmaccrc32checker_syncfifo_wrport_adr <= liteethmaccrc32checker_syncfifo_produce;
|
|
end
|
|
end
|
|
assign liteethmaccrc32checker_syncfifo_wrport_dat_w = liteethmaccrc32checker_syncfifo_syncfifo_din;
|
|
assign liteethmaccrc32checker_syncfifo_wrport_we = (liteethmaccrc32checker_syncfifo_syncfifo_we & (liteethmaccrc32checker_syncfifo_syncfifo_writable | liteethmaccrc32checker_syncfifo_replace));
|
|
assign liteethmaccrc32checker_syncfifo_do_read = (liteethmaccrc32checker_syncfifo_syncfifo_readable & liteethmaccrc32checker_syncfifo_syncfifo_re);
|
|
assign liteethmaccrc32checker_syncfifo_rdport_adr = liteethmaccrc32checker_syncfifo_consume;
|
|
assign liteethmaccrc32checker_syncfifo_syncfifo_dout = liteethmaccrc32checker_syncfifo_rdport_dat_r;
|
|
assign liteethmaccrc32checker_syncfifo_syncfifo_writable = (liteethmaccrc32checker_syncfifo_level != 3'd5);
|
|
assign liteethmaccrc32checker_syncfifo_syncfifo_readable = (liteethmaccrc32checker_syncfifo_level != 1'd0);
|
|
always @(*) begin
|
|
liteethmaccrc32checker_crc_ce <= 1'd0;
|
|
liteethmaccrc32checker_crc_reset <= 1'd0;
|
|
subfragments_liteethmaccrc32checker_next_state <= 2'd0;
|
|
liteethmaccrc32checker_fifo_reset <= 1'd0;
|
|
subfragments_liteethmaccrc32checker_next_state <= subfragments_liteethmaccrc32checker_state;
|
|
case (subfragments_liteethmaccrc32checker_state)
|
|
1'd1: begin
|
|
if ((liteethmaccrc32checker_sink_sink_valid & liteethmaccrc32checker_sink_sink_ready)) begin
|
|
liteethmaccrc32checker_crc_ce <= 1'd1;
|
|
subfragments_liteethmaccrc32checker_next_state <= 2'd2;
|
|
end
|
|
end
|
|
2'd2: begin
|
|
if ((liteethmaccrc32checker_sink_sink_valid & liteethmaccrc32checker_sink_sink_ready)) begin
|
|
liteethmaccrc32checker_crc_ce <= 1'd1;
|
|
if (liteethmaccrc32checker_sink_sink_last) begin
|
|
subfragments_liteethmaccrc32checker_next_state <= 1'd0;
|
|
end
|
|
end
|
|
end
|
|
default: begin
|
|
liteethmaccrc32checker_crc_reset <= 1'd1;
|
|
liteethmaccrc32checker_fifo_reset <= 1'd1;
|
|
subfragments_liteethmaccrc32checker_next_state <= 1'd1;
|
|
end
|
|
endcase
|
|
end
|
|
assign crc32_checker_sink_ready = ((~crc32_checker_source_valid) | crc32_checker_source_ready);
|
|
assign ps_preamble_error_o = (ps_preamble_error_toggle_o ^ ps_preamble_error_toggle_o_r);
|
|
assign ps_crc_error_o = (ps_crc_error_toggle_o ^ ps_crc_error_toggle_o_r);
|
|
assign padding_inserter_counter_done = (padding_inserter_counter >= 6'd59);
|
|
always @(*) begin
|
|
padding_inserter_source_valid <= 1'd0;
|
|
padding_inserter_counter_liteethmacpaddinginserter_next_value_ce <= 1'd0;
|
|
padding_inserter_source_first <= 1'd0;
|
|
padding_inserter_source_last <= 1'd0;
|
|
padding_inserter_source_payload_data <= 8'd0;
|
|
padding_inserter_source_payload_last_be <= 1'd0;
|
|
padding_inserter_source_payload_error <= 1'd0;
|
|
padding_inserter_sink_ready <= 1'd0;
|
|
subfragments_liteethmacpaddinginserter_next_state <= 1'd0;
|
|
padding_inserter_counter_liteethmacpaddinginserter_next_value <= 16'd0;
|
|
subfragments_liteethmacpaddinginserter_next_state <= subfragments_liteethmacpaddinginserter_state;
|
|
case (subfragments_liteethmacpaddinginserter_state)
|
|
1'd1: begin
|
|
padding_inserter_source_valid <= 1'd1;
|
|
padding_inserter_source_last <= padding_inserter_counter_done;
|
|
padding_inserter_source_payload_data <= 1'd0;
|
|
if ((padding_inserter_source_valid & padding_inserter_source_ready)) begin
|
|
padding_inserter_counter_liteethmacpaddinginserter_next_value <= (padding_inserter_counter + 1'd1);
|
|
padding_inserter_counter_liteethmacpaddinginserter_next_value_ce <= 1'd1;
|
|
if (padding_inserter_counter_done) begin
|
|
padding_inserter_counter_liteethmacpaddinginserter_next_value <= 1'd0;
|
|
padding_inserter_counter_liteethmacpaddinginserter_next_value_ce <= 1'd1;
|
|
subfragments_liteethmacpaddinginserter_next_state <= 1'd0;
|
|
end
|
|
end
|
|
end
|
|
default: begin
|
|
padding_inserter_source_valid <= padding_inserter_sink_valid;
|
|
padding_inserter_sink_ready <= padding_inserter_source_ready;
|
|
padding_inserter_source_first <= padding_inserter_sink_first;
|
|
padding_inserter_source_last <= padding_inserter_sink_last;
|
|
padding_inserter_source_payload_data <= padding_inserter_sink_payload_data;
|
|
padding_inserter_source_payload_last_be <= padding_inserter_sink_payload_last_be;
|
|
padding_inserter_source_payload_error <= padding_inserter_sink_payload_error;
|
|
if ((padding_inserter_source_valid & padding_inserter_source_ready)) begin
|
|
padding_inserter_counter_liteethmacpaddinginserter_next_value <= (padding_inserter_counter + 1'd1);
|
|
padding_inserter_counter_liteethmacpaddinginserter_next_value_ce <= 1'd1;
|
|
if (padding_inserter_sink_last) begin
|
|
if ((~padding_inserter_counter_done)) begin
|
|
padding_inserter_source_last <= 1'd0;
|
|
subfragments_liteethmacpaddinginserter_next_state <= 1'd1;
|
|
end else begin
|
|
padding_inserter_counter_liteethmacpaddinginserter_next_value <= 1'd0;
|
|
padding_inserter_counter_liteethmacpaddinginserter_next_value_ce <= 1'd1;
|
|
end
|
|
end
|
|
end
|
|
end
|
|
endcase
|
|
end
|
|
assign padding_checker_source_valid = padding_checker_sink_valid;
|
|
assign padding_checker_sink_ready = padding_checker_source_ready;
|
|
assign padding_checker_source_first = padding_checker_sink_first;
|
|
assign padding_checker_source_last = padding_checker_sink_last;
|
|
assign padding_checker_source_payload_data = padding_checker_sink_payload_data;
|
|
assign padding_checker_source_payload_last_be = padding_checker_sink_payload_last_be;
|
|
assign padding_checker_source_payload_error = padding_checker_sink_payload_error;
|
|
always @(*) begin
|
|
tx_last_be_source_payload_data <= 8'd0;
|
|
subfragments_liteethmactxlastbe_next_state <= 1'd0;
|
|
tx_last_be_source_payload_error <= 1'd0;
|
|
tx_last_be_sink_ready <= 1'd0;
|
|
tx_last_be_source_valid <= 1'd0;
|
|
tx_last_be_source_first <= 1'd0;
|
|
tx_last_be_source_last <= 1'd0;
|
|
subfragments_liteethmactxlastbe_next_state <= subfragments_liteethmactxlastbe_state;
|
|
case (subfragments_liteethmactxlastbe_state)
|
|
1'd1: begin
|
|
tx_last_be_sink_ready <= 1'd1;
|
|
if ((tx_last_be_sink_valid & tx_last_be_sink_last)) begin
|
|
subfragments_liteethmactxlastbe_next_state <= 1'd0;
|
|
end
|
|
end
|
|
default: begin
|
|
tx_last_be_source_valid <= tx_last_be_sink_valid;
|
|
tx_last_be_sink_ready <= tx_last_be_source_ready;
|
|
tx_last_be_source_first <= tx_last_be_sink_first;
|
|
tx_last_be_source_payload_data <= tx_last_be_sink_payload_data;
|
|
tx_last_be_source_payload_error <= tx_last_be_sink_payload_error;
|
|
tx_last_be_source_last <= tx_last_be_sink_payload_last_be;
|
|
if ((tx_last_be_sink_valid & tx_last_be_sink_ready)) begin
|
|
if ((tx_last_be_sink_payload_last_be & (~tx_last_be_sink_last))) begin
|
|
subfragments_liteethmactxlastbe_next_state <= 1'd1;
|
|
end
|
|
end
|
|
end
|
|
endcase
|
|
end
|
|
assign rx_last_be_source_valid = rx_last_be_sink_valid;
|
|
assign rx_last_be_sink_ready = rx_last_be_source_ready;
|
|
assign rx_last_be_source_first = rx_last_be_sink_first;
|
|
assign rx_last_be_source_last = rx_last_be_sink_last;
|
|
assign rx_last_be_source_payload_data = rx_last_be_sink_payload_data;
|
|
assign rx_last_be_source_payload_error = rx_last_be_sink_payload_error;
|
|
always @(*) begin
|
|
rx_last_be_source_payload_last_be <= 1'd0;
|
|
rx_last_be_source_payload_last_be <= rx_last_be_sink_payload_last_be;
|
|
rx_last_be_source_payload_last_be <= rx_last_be_sink_last;
|
|
end
|
|
assign tx_converter_converter_sink_valid = tx_converter_sink_valid;
|
|
assign tx_converter_converter_sink_first = tx_converter_sink_first;
|
|
assign tx_converter_converter_sink_last = tx_converter_sink_last;
|
|
assign tx_converter_sink_ready = tx_converter_converter_sink_ready;
|
|
always @(*) begin
|
|
tx_converter_converter_sink_payload_data <= 40'd0;
|
|
tx_converter_converter_sink_payload_data[7:0] <= tx_converter_sink_payload_data[7:0];
|
|
tx_converter_converter_sink_payload_data[8] <= tx_converter_sink_payload_last_be[0];
|
|
tx_converter_converter_sink_payload_data[9] <= tx_converter_sink_payload_error[0];
|
|
tx_converter_converter_sink_payload_data[17:10] <= tx_converter_sink_payload_data[15:8];
|
|
tx_converter_converter_sink_payload_data[18] <= tx_converter_sink_payload_last_be[1];
|
|
tx_converter_converter_sink_payload_data[19] <= tx_converter_sink_payload_error[1];
|
|
tx_converter_converter_sink_payload_data[27:20] <= tx_converter_sink_payload_data[23:16];
|
|
tx_converter_converter_sink_payload_data[28] <= tx_converter_sink_payload_last_be[2];
|
|
tx_converter_converter_sink_payload_data[29] <= tx_converter_sink_payload_error[2];
|
|
tx_converter_converter_sink_payload_data[37:30] <= tx_converter_sink_payload_data[31:24];
|
|
tx_converter_converter_sink_payload_data[38] <= tx_converter_sink_payload_last_be[3];
|
|
tx_converter_converter_sink_payload_data[39] <= tx_converter_sink_payload_error[3];
|
|
end
|
|
assign tx_converter_source_valid = tx_converter_source_source_valid;
|
|
assign tx_converter_source_first = tx_converter_source_source_first;
|
|
assign tx_converter_source_last = tx_converter_source_source_last;
|
|
assign tx_converter_source_source_ready = tx_converter_source_ready;
|
|
assign {tx_converter_source_payload_error, tx_converter_source_payload_last_be, tx_converter_source_payload_data} = tx_converter_source_source_payload_data;
|
|
assign tx_converter_source_source_valid = tx_converter_converter_source_valid;
|
|
assign tx_converter_converter_source_ready = tx_converter_source_source_ready;
|
|
assign tx_converter_source_source_first = tx_converter_converter_source_first;
|
|
assign tx_converter_source_source_last = tx_converter_converter_source_last;
|
|
assign tx_converter_source_source_payload_data = tx_converter_converter_source_payload_data;
|
|
assign tx_converter_converter_first = (tx_converter_converter_mux == 1'd0);
|
|
assign tx_converter_converter_last = (tx_converter_converter_mux == 2'd3);
|
|
assign tx_converter_converter_source_valid = tx_converter_converter_sink_valid;
|
|
assign tx_converter_converter_source_first = (tx_converter_converter_sink_first & tx_converter_converter_first);
|
|
assign tx_converter_converter_source_last = (tx_converter_converter_sink_last & tx_converter_converter_last);
|
|
assign tx_converter_converter_sink_ready = (tx_converter_converter_last & tx_converter_converter_source_ready);
|
|
always @(*) begin
|
|
tx_converter_converter_source_payload_data <= 10'd0;
|
|
case (tx_converter_converter_mux)
|
|
1'd0: begin
|
|
tx_converter_converter_source_payload_data <= tx_converter_converter_sink_payload_data[9:0];
|
|
end
|
|
1'd1: begin
|
|
tx_converter_converter_source_payload_data <= tx_converter_converter_sink_payload_data[19:10];
|
|
end
|
|
2'd2: begin
|
|
tx_converter_converter_source_payload_data <= tx_converter_converter_sink_payload_data[29:20];
|
|
end
|
|
default: begin
|
|
tx_converter_converter_source_payload_data <= tx_converter_converter_sink_payload_data[39:30];
|
|
end
|
|
endcase
|
|
end
|
|
assign tx_converter_converter_source_payload_valid_token_count = tx_converter_converter_last;
|
|
assign rx_converter_converter_sink_valid = rx_converter_sink_valid;
|
|
assign rx_converter_converter_sink_first = rx_converter_sink_first;
|
|
assign rx_converter_converter_sink_last = rx_converter_sink_last;
|
|
assign rx_converter_sink_ready = rx_converter_converter_sink_ready;
|
|
assign rx_converter_converter_sink_payload_data = {rx_converter_sink_payload_error, rx_converter_sink_payload_last_be, rx_converter_sink_payload_data};
|
|
assign rx_converter_source_valid = rx_converter_source_source_valid;
|
|
assign rx_converter_source_first = rx_converter_source_source_first;
|
|
assign rx_converter_source_last = rx_converter_source_source_last;
|
|
assign rx_converter_source_source_ready = rx_converter_source_ready;
|
|
always @(*) begin
|
|
rx_converter_source_payload_data <= 32'd0;
|
|
rx_converter_source_payload_data[7:0] <= rx_converter_source_source_payload_data[7:0];
|
|
rx_converter_source_payload_data[15:8] <= rx_converter_source_source_payload_data[17:10];
|
|
rx_converter_source_payload_data[23:16] <= rx_converter_source_source_payload_data[27:20];
|
|
rx_converter_source_payload_data[31:24] <= rx_converter_source_source_payload_data[37:30];
|
|
end
|
|
always @(*) begin
|
|
rx_converter_source_payload_last_be <= 4'd0;
|
|
rx_converter_source_payload_last_be[0] <= rx_converter_source_source_payload_data[8];
|
|
rx_converter_source_payload_last_be[1] <= rx_converter_source_source_payload_data[18];
|
|
rx_converter_source_payload_last_be[2] <= rx_converter_source_source_payload_data[28];
|
|
rx_converter_source_payload_last_be[3] <= rx_converter_source_source_payload_data[38];
|
|
end
|
|
always @(*) begin
|
|
rx_converter_source_payload_error <= 4'd0;
|
|
rx_converter_source_payload_error[0] <= rx_converter_source_source_payload_data[9];
|
|
rx_converter_source_payload_error[1] <= rx_converter_source_source_payload_data[19];
|
|
rx_converter_source_payload_error[2] <= rx_converter_source_source_payload_data[29];
|
|
rx_converter_source_payload_error[3] <= rx_converter_source_source_payload_data[39];
|
|
end
|
|
assign rx_converter_source_source_valid = rx_converter_converter_source_valid;
|
|
assign rx_converter_converter_source_ready = rx_converter_source_source_ready;
|
|
assign rx_converter_source_source_first = rx_converter_converter_source_first;
|
|
assign rx_converter_source_source_last = rx_converter_converter_source_last;
|
|
assign rx_converter_source_source_payload_data = rx_converter_converter_source_payload_data;
|
|
assign rx_converter_converter_sink_ready = ((~rx_converter_converter_strobe_all) | rx_converter_converter_source_ready);
|
|
assign rx_converter_converter_source_valid = rx_converter_converter_strobe_all;
|
|
assign rx_converter_converter_load_part = (rx_converter_converter_sink_valid & rx_converter_converter_sink_ready);
|
|
assign tx_cdc_cdc_sink_valid = tx_cdc_sink_sink_valid;
|
|
assign tx_cdc_sink_sink_ready = tx_cdc_cdc_sink_ready;
|
|
assign tx_cdc_cdc_sink_first = tx_cdc_sink_sink_first;
|
|
assign tx_cdc_cdc_sink_last = tx_cdc_sink_sink_last;
|
|
assign tx_cdc_cdc_sink_payload_data = tx_cdc_sink_sink_payload_data;
|
|
assign tx_cdc_cdc_sink_payload_last_be = tx_cdc_sink_sink_payload_last_be;
|
|
assign tx_cdc_cdc_sink_payload_error = tx_cdc_sink_sink_payload_error;
|
|
assign tx_cdc_source_source_valid = tx_cdc_cdc_source_valid;
|
|
assign tx_cdc_cdc_source_ready = tx_cdc_source_source_ready;
|
|
assign tx_cdc_source_source_first = tx_cdc_cdc_source_first;
|
|
assign tx_cdc_source_source_last = tx_cdc_cdc_source_last;
|
|
assign tx_cdc_source_source_payload_data = tx_cdc_cdc_source_payload_data;
|
|
assign tx_cdc_source_source_payload_last_be = tx_cdc_cdc_source_payload_last_be;
|
|
assign tx_cdc_source_source_payload_error = tx_cdc_cdc_source_payload_error;
|
|
assign tx_cdc_cdc_asyncfifo_din = {tx_cdc_cdc_fifo_in_last, tx_cdc_cdc_fifo_in_first, tx_cdc_cdc_fifo_in_payload_error, tx_cdc_cdc_fifo_in_payload_last_be, tx_cdc_cdc_fifo_in_payload_data};
|
|
assign {tx_cdc_cdc_fifo_out_last, tx_cdc_cdc_fifo_out_first, tx_cdc_cdc_fifo_out_payload_error, tx_cdc_cdc_fifo_out_payload_last_be, tx_cdc_cdc_fifo_out_payload_data} = tx_cdc_cdc_asyncfifo_dout;
|
|
assign tx_cdc_cdc_sink_ready = tx_cdc_cdc_asyncfifo_writable;
|
|
assign tx_cdc_cdc_asyncfifo_we = tx_cdc_cdc_sink_valid;
|
|
assign tx_cdc_cdc_fifo_in_first = tx_cdc_cdc_sink_first;
|
|
assign tx_cdc_cdc_fifo_in_last = tx_cdc_cdc_sink_last;
|
|
assign tx_cdc_cdc_fifo_in_payload_data = tx_cdc_cdc_sink_payload_data;
|
|
assign tx_cdc_cdc_fifo_in_payload_last_be = tx_cdc_cdc_sink_payload_last_be;
|
|
assign tx_cdc_cdc_fifo_in_payload_error = tx_cdc_cdc_sink_payload_error;
|
|
assign tx_cdc_cdc_source_valid = tx_cdc_cdc_asyncfifo_readable;
|
|
assign tx_cdc_cdc_source_first = tx_cdc_cdc_fifo_out_first;
|
|
assign tx_cdc_cdc_source_last = tx_cdc_cdc_fifo_out_last;
|
|
assign tx_cdc_cdc_source_payload_data = tx_cdc_cdc_fifo_out_payload_data;
|
|
assign tx_cdc_cdc_source_payload_last_be = tx_cdc_cdc_fifo_out_payload_last_be;
|
|
assign tx_cdc_cdc_source_payload_error = tx_cdc_cdc_fifo_out_payload_error;
|
|
assign tx_cdc_cdc_asyncfifo_re = tx_cdc_cdc_source_ready;
|
|
assign tx_cdc_cdc_graycounter0_ce = (tx_cdc_cdc_asyncfifo_writable & tx_cdc_cdc_asyncfifo_we);
|
|
assign tx_cdc_cdc_graycounter1_ce = (tx_cdc_cdc_asyncfifo_readable & tx_cdc_cdc_asyncfifo_re);
|
|
assign tx_cdc_cdc_asyncfifo_writable = (((tx_cdc_cdc_graycounter0_q[5] == tx_cdc_cdc_consume_wdomain[5]) | (tx_cdc_cdc_graycounter0_q[4] == tx_cdc_cdc_consume_wdomain[4])) | (tx_cdc_cdc_graycounter0_q[3:0] != tx_cdc_cdc_consume_wdomain[3:0]));
|
|
assign tx_cdc_cdc_asyncfifo_readable = (tx_cdc_cdc_graycounter1_q != tx_cdc_cdc_produce_rdomain);
|
|
assign tx_cdc_cdc_wrport_adr = tx_cdc_cdc_graycounter0_q_binary[4:0];
|
|
assign tx_cdc_cdc_wrport_dat_w = tx_cdc_cdc_asyncfifo_din;
|
|
assign tx_cdc_cdc_wrport_we = tx_cdc_cdc_graycounter0_ce;
|
|
assign tx_cdc_cdc_rdport_adr = tx_cdc_cdc_graycounter1_q_next_binary[4:0];
|
|
assign tx_cdc_cdc_asyncfifo_dout = tx_cdc_cdc_rdport_dat_r;
|
|
always @(*) begin
|
|
tx_cdc_cdc_graycounter0_q_next_binary <= 6'd0;
|
|
if (tx_cdc_cdc_graycounter0_ce) begin
|
|
tx_cdc_cdc_graycounter0_q_next_binary <= (tx_cdc_cdc_graycounter0_q_binary + 1'd1);
|
|
end else begin
|
|
tx_cdc_cdc_graycounter0_q_next_binary <= tx_cdc_cdc_graycounter0_q_binary;
|
|
end
|
|
end
|
|
assign tx_cdc_cdc_graycounter0_q_next = (tx_cdc_cdc_graycounter0_q_next_binary ^ tx_cdc_cdc_graycounter0_q_next_binary[5:1]);
|
|
always @(*) begin
|
|
tx_cdc_cdc_graycounter1_q_next_binary <= 6'd0;
|
|
if (tx_cdc_cdc_graycounter1_ce) begin
|
|
tx_cdc_cdc_graycounter1_q_next_binary <= (tx_cdc_cdc_graycounter1_q_binary + 1'd1);
|
|
end else begin
|
|
tx_cdc_cdc_graycounter1_q_next_binary <= tx_cdc_cdc_graycounter1_q_binary;
|
|
end
|
|
end
|
|
assign tx_cdc_cdc_graycounter1_q_next = (tx_cdc_cdc_graycounter1_q_next_binary ^ tx_cdc_cdc_graycounter1_q_next_binary[5:1]);
|
|
assign rx_cdc_cdc_sink_valid = rx_cdc_sink_sink_valid;
|
|
assign rx_cdc_sink_sink_ready = rx_cdc_cdc_sink_ready;
|
|
assign rx_cdc_cdc_sink_first = rx_cdc_sink_sink_first;
|
|
assign rx_cdc_cdc_sink_last = rx_cdc_sink_sink_last;
|
|
assign rx_cdc_cdc_sink_payload_data = rx_cdc_sink_sink_payload_data;
|
|
assign rx_cdc_cdc_sink_payload_last_be = rx_cdc_sink_sink_payload_last_be;
|
|
assign rx_cdc_cdc_sink_payload_error = rx_cdc_sink_sink_payload_error;
|
|
assign rx_cdc_source_source_valid = rx_cdc_cdc_source_valid;
|
|
assign rx_cdc_cdc_source_ready = rx_cdc_source_source_ready;
|
|
assign rx_cdc_source_source_first = rx_cdc_cdc_source_first;
|
|
assign rx_cdc_source_source_last = rx_cdc_cdc_source_last;
|
|
assign rx_cdc_source_source_payload_data = rx_cdc_cdc_source_payload_data;
|
|
assign rx_cdc_source_source_payload_last_be = rx_cdc_cdc_source_payload_last_be;
|
|
assign rx_cdc_source_source_payload_error = rx_cdc_cdc_source_payload_error;
|
|
assign rx_cdc_cdc_asyncfifo_din = {rx_cdc_cdc_fifo_in_last, rx_cdc_cdc_fifo_in_first, rx_cdc_cdc_fifo_in_payload_error, rx_cdc_cdc_fifo_in_payload_last_be, rx_cdc_cdc_fifo_in_payload_data};
|
|
assign {rx_cdc_cdc_fifo_out_last, rx_cdc_cdc_fifo_out_first, rx_cdc_cdc_fifo_out_payload_error, rx_cdc_cdc_fifo_out_payload_last_be, rx_cdc_cdc_fifo_out_payload_data} = rx_cdc_cdc_asyncfifo_dout;
|
|
assign rx_cdc_cdc_sink_ready = rx_cdc_cdc_asyncfifo_writable;
|
|
assign rx_cdc_cdc_asyncfifo_we = rx_cdc_cdc_sink_valid;
|
|
assign rx_cdc_cdc_fifo_in_first = rx_cdc_cdc_sink_first;
|
|
assign rx_cdc_cdc_fifo_in_last = rx_cdc_cdc_sink_last;
|
|
assign rx_cdc_cdc_fifo_in_payload_data = rx_cdc_cdc_sink_payload_data;
|
|
assign rx_cdc_cdc_fifo_in_payload_last_be = rx_cdc_cdc_sink_payload_last_be;
|
|
assign rx_cdc_cdc_fifo_in_payload_error = rx_cdc_cdc_sink_payload_error;
|
|
assign rx_cdc_cdc_source_valid = rx_cdc_cdc_asyncfifo_readable;
|
|
assign rx_cdc_cdc_source_first = rx_cdc_cdc_fifo_out_first;
|
|
assign rx_cdc_cdc_source_last = rx_cdc_cdc_fifo_out_last;
|
|
assign rx_cdc_cdc_source_payload_data = rx_cdc_cdc_fifo_out_payload_data;
|
|
assign rx_cdc_cdc_source_payload_last_be = rx_cdc_cdc_fifo_out_payload_last_be;
|
|
assign rx_cdc_cdc_source_payload_error = rx_cdc_cdc_fifo_out_payload_error;
|
|
assign rx_cdc_cdc_asyncfifo_re = rx_cdc_cdc_source_ready;
|
|
assign rx_cdc_cdc_graycounter0_ce = (rx_cdc_cdc_asyncfifo_writable & rx_cdc_cdc_asyncfifo_we);
|
|
assign rx_cdc_cdc_graycounter1_ce = (rx_cdc_cdc_asyncfifo_readable & rx_cdc_cdc_asyncfifo_re);
|
|
assign rx_cdc_cdc_asyncfifo_writable = (((rx_cdc_cdc_graycounter0_q[5] == rx_cdc_cdc_consume_wdomain[5]) | (rx_cdc_cdc_graycounter0_q[4] == rx_cdc_cdc_consume_wdomain[4])) | (rx_cdc_cdc_graycounter0_q[3:0] != rx_cdc_cdc_consume_wdomain[3:0]));
|
|
assign rx_cdc_cdc_asyncfifo_readable = (rx_cdc_cdc_graycounter1_q != rx_cdc_cdc_produce_rdomain);
|
|
assign rx_cdc_cdc_wrport_adr = rx_cdc_cdc_graycounter0_q_binary[4:0];
|
|
assign rx_cdc_cdc_wrport_dat_w = rx_cdc_cdc_asyncfifo_din;
|
|
assign rx_cdc_cdc_wrport_we = rx_cdc_cdc_graycounter0_ce;
|
|
assign rx_cdc_cdc_rdport_adr = rx_cdc_cdc_graycounter1_q_next_binary[4:0];
|
|
assign rx_cdc_cdc_asyncfifo_dout = rx_cdc_cdc_rdport_dat_r;
|
|
always @(*) begin
|
|
rx_cdc_cdc_graycounter0_q_next_binary <= 6'd0;
|
|
if (rx_cdc_cdc_graycounter0_ce) begin
|
|
rx_cdc_cdc_graycounter0_q_next_binary <= (rx_cdc_cdc_graycounter0_q_binary + 1'd1);
|
|
end else begin
|
|
rx_cdc_cdc_graycounter0_q_next_binary <= rx_cdc_cdc_graycounter0_q_binary;
|
|
end
|
|
end
|
|
assign rx_cdc_cdc_graycounter0_q_next = (rx_cdc_cdc_graycounter0_q_next_binary ^ rx_cdc_cdc_graycounter0_q_next_binary[5:1]);
|
|
always @(*) begin
|
|
rx_cdc_cdc_graycounter1_q_next_binary <= 6'd0;
|
|
if (rx_cdc_cdc_graycounter1_ce) begin
|
|
rx_cdc_cdc_graycounter1_q_next_binary <= (rx_cdc_cdc_graycounter1_q_binary + 1'd1);
|
|
end else begin
|
|
rx_cdc_cdc_graycounter1_q_next_binary <= rx_cdc_cdc_graycounter1_q_binary;
|
|
end
|
|
end
|
|
assign rx_cdc_cdc_graycounter1_q_next = (rx_cdc_cdc_graycounter1_q_next_binary ^ rx_cdc_cdc_graycounter1_q_next_binary[5:1]);
|
|
assign tx_converter_sink_valid = tx_cdc_source_source_valid;
|
|
assign tx_cdc_source_source_ready = tx_converter_sink_ready;
|
|
assign tx_converter_sink_first = tx_cdc_source_source_first;
|
|
assign tx_converter_sink_last = tx_cdc_source_source_last;
|
|
assign tx_converter_sink_payload_data = tx_cdc_source_source_payload_data;
|
|
assign tx_converter_sink_payload_last_be = tx_cdc_source_source_payload_last_be;
|
|
assign tx_converter_sink_payload_error = tx_cdc_source_source_payload_error;
|
|
assign tx_last_be_sink_valid = tx_converter_source_valid;
|
|
assign tx_converter_source_ready = tx_last_be_sink_ready;
|
|
assign tx_last_be_sink_first = tx_converter_source_first;
|
|
assign tx_last_be_sink_last = tx_converter_source_last;
|
|
assign tx_last_be_sink_payload_data = tx_converter_source_payload_data;
|
|
assign tx_last_be_sink_payload_last_be = tx_converter_source_payload_last_be;
|
|
assign tx_last_be_sink_payload_error = tx_converter_source_payload_error;
|
|
assign padding_inserter_sink_valid = tx_last_be_source_valid;
|
|
assign tx_last_be_source_ready = padding_inserter_sink_ready;
|
|
assign padding_inserter_sink_first = tx_last_be_source_first;
|
|
assign padding_inserter_sink_last = tx_last_be_source_last;
|
|
assign padding_inserter_sink_payload_data = tx_last_be_source_payload_data;
|
|
assign padding_inserter_sink_payload_last_be = tx_last_be_source_payload_last_be;
|
|
assign padding_inserter_sink_payload_error = tx_last_be_source_payload_error;
|
|
assign crc32_inserter_sink_valid = padding_inserter_source_valid;
|
|
assign padding_inserter_source_ready = crc32_inserter_sink_ready;
|
|
assign crc32_inserter_sink_first = padding_inserter_source_first;
|
|
assign crc32_inserter_sink_last = padding_inserter_source_last;
|
|
assign crc32_inserter_sink_payload_data = padding_inserter_source_payload_data;
|
|
assign crc32_inserter_sink_payload_last_be = padding_inserter_source_payload_last_be;
|
|
assign crc32_inserter_sink_payload_error = padding_inserter_source_payload_error;
|
|
assign preamble_inserter_sink_valid = liteethmaccrc32inserter_source_valid;
|
|
assign liteethmaccrc32inserter_source_ready = preamble_inserter_sink_ready;
|
|
assign preamble_inserter_sink_first = liteethmaccrc32inserter_source_first;
|
|
assign preamble_inserter_sink_last = liteethmaccrc32inserter_source_last;
|
|
assign preamble_inserter_sink_payload_data = liteethmaccrc32inserter_source_payload_data;
|
|
assign preamble_inserter_sink_payload_last_be = liteethmaccrc32inserter_source_payload_last_be;
|
|
assign preamble_inserter_sink_payload_error = liteethmaccrc32inserter_source_payload_error;
|
|
assign tx_gap_inserter_sink_valid = preamble_inserter_source_valid;
|
|
assign preamble_inserter_source_ready = tx_gap_inserter_sink_ready;
|
|
assign tx_gap_inserter_sink_first = preamble_inserter_source_first;
|
|
assign tx_gap_inserter_sink_last = preamble_inserter_source_last;
|
|
assign tx_gap_inserter_sink_payload_data = preamble_inserter_source_payload_data;
|
|
assign tx_gap_inserter_sink_payload_last_be = preamble_inserter_source_payload_last_be;
|
|
assign tx_gap_inserter_sink_payload_error = preamble_inserter_source_payload_error;
|
|
assign maccore_ethphy_liteethphygmiimiitx_sink_sink_valid0 = tx_gap_inserter_source_valid;
|
|
assign tx_gap_inserter_source_ready = maccore_ethphy_liteethphygmiimiitx_sink_sink_ready0;
|
|
assign maccore_ethphy_liteethphygmiimiitx_sink_sink_first0 = tx_gap_inserter_source_first;
|
|
assign maccore_ethphy_liteethphygmiimiitx_sink_sink_last0 = tx_gap_inserter_source_last;
|
|
assign maccore_ethphy_liteethphygmiimiitx_sink_sink_payload_data0 = tx_gap_inserter_source_payload_data;
|
|
assign maccore_ethphy_liteethphygmiimiitx_sink_sink_payload_last_be0 = tx_gap_inserter_source_payload_last_be;
|
|
assign maccore_ethphy_liteethphygmiimiitx_sink_sink_payload_error0 = tx_gap_inserter_source_payload_error;
|
|
assign preamble_checker_sink_valid = maccore_ethphy_liteethphygmiimiirx_source_source_valid0;
|
|
assign maccore_ethphy_liteethphygmiimiirx_source_source_ready0 = preamble_checker_sink_ready;
|
|
assign preamble_checker_sink_first = maccore_ethphy_liteethphygmiimiirx_source_source_first0;
|
|
assign preamble_checker_sink_last = maccore_ethphy_liteethphygmiimiirx_source_source_last0;
|
|
assign preamble_checker_sink_payload_data = maccore_ethphy_liteethphygmiimiirx_source_source_payload_data0;
|
|
assign preamble_checker_sink_payload_last_be = maccore_ethphy_liteethphygmiimiirx_source_source_payload_last_be0;
|
|
assign preamble_checker_sink_payload_error = maccore_ethphy_liteethphygmiimiirx_source_source_payload_error0;
|
|
assign crc32_checker_sink_valid = preamble_checker_source_valid;
|
|
assign preamble_checker_source_ready = crc32_checker_sink_ready;
|
|
assign crc32_checker_sink_first = preamble_checker_source_first;
|
|
assign crc32_checker_sink_last = preamble_checker_source_last;
|
|
assign crc32_checker_sink_payload_data = preamble_checker_source_payload_data;
|
|
assign crc32_checker_sink_payload_last_be = preamble_checker_source_payload_last_be;
|
|
assign crc32_checker_sink_payload_error = preamble_checker_source_payload_error;
|
|
assign padding_checker_sink_valid = liteethmaccrc32checker_source_source_valid;
|
|
assign liteethmaccrc32checker_source_source_ready = padding_checker_sink_ready;
|
|
assign padding_checker_sink_first = liteethmaccrc32checker_source_source_first;
|
|
assign padding_checker_sink_last = liteethmaccrc32checker_source_source_last;
|
|
assign padding_checker_sink_payload_data = liteethmaccrc32checker_source_source_payload_data;
|
|
assign padding_checker_sink_payload_last_be = liteethmaccrc32checker_source_source_payload_last_be;
|
|
assign padding_checker_sink_payload_error = liteethmaccrc32checker_source_source_payload_error;
|
|
assign rx_last_be_sink_valid = padding_checker_source_valid;
|
|
assign padding_checker_source_ready = rx_last_be_sink_ready;
|
|
assign rx_last_be_sink_first = padding_checker_source_first;
|
|
assign rx_last_be_sink_last = padding_checker_source_last;
|
|
assign rx_last_be_sink_payload_data = padding_checker_source_payload_data;
|
|
assign rx_last_be_sink_payload_last_be = padding_checker_source_payload_last_be;
|
|
assign rx_last_be_sink_payload_error = padding_checker_source_payload_error;
|
|
assign rx_converter_sink_valid = rx_last_be_source_valid;
|
|
assign rx_last_be_source_ready = rx_converter_sink_ready;
|
|
assign rx_converter_sink_first = rx_last_be_source_first;
|
|
assign rx_converter_sink_last = rx_last_be_source_last;
|
|
assign rx_converter_sink_payload_data = rx_last_be_source_payload_data;
|
|
assign rx_converter_sink_payload_last_be = rx_last_be_source_payload_last_be;
|
|
assign rx_converter_sink_payload_error = rx_last_be_source_payload_error;
|
|
assign rx_cdc_sink_sink_valid = rx_converter_source_valid;
|
|
assign rx_converter_source_ready = rx_cdc_sink_sink_ready;
|
|
assign rx_cdc_sink_sink_first = rx_converter_source_first;
|
|
assign rx_cdc_sink_sink_last = rx_converter_source_last;
|
|
assign rx_cdc_sink_sink_payload_data = rx_converter_source_payload_data;
|
|
assign rx_cdc_sink_sink_payload_last_be = rx_converter_source_payload_last_be;
|
|
assign rx_cdc_sink_sink_payload_error = rx_converter_source_payload_error;
|
|
assign writer_sink_sink_valid = sink_valid;
|
|
assign sink_ready = writer_sink_sink_ready;
|
|
assign writer_sink_sink_first = sink_first;
|
|
assign writer_sink_sink_last = sink_last;
|
|
assign writer_sink_sink_payload_data = sink_payload_data;
|
|
assign writer_sink_sink_payload_last_be = sink_payload_last_be;
|
|
assign writer_sink_sink_payload_error = sink_payload_error;
|
|
assign source_valid = reader_source_source_valid;
|
|
assign reader_source_source_ready = source_ready;
|
|
assign source_first = reader_source_source_first;
|
|
assign source_last = reader_source_source_last;
|
|
assign source_payload_data = reader_source_source_payload_data;
|
|
assign source_payload_last_be = reader_source_source_payload_last_be;
|
|
assign source_payload_error = reader_source_source_payload_error;
|
|
always @(*) begin
|
|
writer_inc <= 3'd0;
|
|
case (writer_sink_sink_payload_last_be)
|
|
1'd1: begin
|
|
writer_inc <= 1'd1;
|
|
end
|
|
2'd2: begin
|
|
writer_inc <= 2'd2;
|
|
end
|
|
3'd4: begin
|
|
writer_inc <= 2'd3;
|
|
end
|
|
default: begin
|
|
writer_inc <= 3'd4;
|
|
end
|
|
endcase
|
|
end
|
|
assign writer_stat_fifo_sink_payload_slot = writer_slot;
|
|
assign writer_stat_fifo_sink_payload_length = writer_counter;
|
|
assign writer_stat_fifo_source_ready = writer_available_clear;
|
|
assign writer_available_trigger = writer_stat_fifo_source_valid;
|
|
assign writer_slot_status = writer_stat_fifo_source_payload_slot;
|
|
assign writer_length_status = writer_stat_fifo_source_payload_length;
|
|
always @(*) begin
|
|
writer_memory1_adr <= 9'd0;
|
|
writer_memory1_we <= 1'd0;
|
|
writer_memory0_adr <= 9'd0;
|
|
writer_memory1_dat_w <= 32'd0;
|
|
writer_memory0_we <= 1'd0;
|
|
writer_memory0_dat_w <= 32'd0;
|
|
case (writer_slot)
|
|
1'd0: begin
|
|
writer_memory0_adr <= writer_counter[31:2];
|
|
writer_memory0_dat_w <= writer_sink_sink_payload_data;
|
|
if ((writer_sink_sink_valid & writer_ongoing)) begin
|
|
writer_memory0_we <= 4'd15;
|
|
end
|
|
end
|
|
1'd1: begin
|
|
writer_memory1_adr <= writer_counter[31:2];
|
|
writer_memory1_dat_w <= writer_sink_sink_payload_data;
|
|
if ((writer_sink_sink_valid & writer_ongoing)) begin
|
|
writer_memory1_we <= 4'd15;
|
|
end
|
|
end
|
|
endcase
|
|
end
|
|
assign writer_available0 = writer_available_status;
|
|
assign writer_available1 = writer_available_pending;
|
|
always @(*) begin
|
|
writer_available_clear <= 1'd0;
|
|
if ((writer_pending_re & writer_pending_r)) begin
|
|
writer_available_clear <= 1'd1;
|
|
end
|
|
end
|
|
assign writer_irq = (writer_pending_status & writer_enable_storage);
|
|
assign writer_available_status = writer_available_trigger;
|
|
assign writer_available_pending = writer_available_trigger;
|
|
assign writer_stat_fifo_syncfifo_din = {writer_stat_fifo_fifo_in_last, writer_stat_fifo_fifo_in_first, writer_stat_fifo_fifo_in_payload_length, writer_stat_fifo_fifo_in_payload_slot};
|
|
assign {writer_stat_fifo_fifo_out_last, writer_stat_fifo_fifo_out_first, writer_stat_fifo_fifo_out_payload_length, writer_stat_fifo_fifo_out_payload_slot} = writer_stat_fifo_syncfifo_dout;
|
|
assign writer_stat_fifo_sink_ready = writer_stat_fifo_syncfifo_writable;
|
|
assign writer_stat_fifo_syncfifo_we = writer_stat_fifo_sink_valid;
|
|
assign writer_stat_fifo_fifo_in_first = writer_stat_fifo_sink_first;
|
|
assign writer_stat_fifo_fifo_in_last = writer_stat_fifo_sink_last;
|
|
assign writer_stat_fifo_fifo_in_payload_slot = writer_stat_fifo_sink_payload_slot;
|
|
assign writer_stat_fifo_fifo_in_payload_length = writer_stat_fifo_sink_payload_length;
|
|
assign writer_stat_fifo_source_valid = writer_stat_fifo_syncfifo_readable;
|
|
assign writer_stat_fifo_source_first = writer_stat_fifo_fifo_out_first;
|
|
assign writer_stat_fifo_source_last = writer_stat_fifo_fifo_out_last;
|
|
assign writer_stat_fifo_source_payload_slot = writer_stat_fifo_fifo_out_payload_slot;
|
|
assign writer_stat_fifo_source_payload_length = writer_stat_fifo_fifo_out_payload_length;
|
|
assign writer_stat_fifo_syncfifo_re = writer_stat_fifo_source_ready;
|
|
always @(*) begin
|
|
writer_stat_fifo_wrport_adr <= 1'd0;
|
|
if (writer_stat_fifo_replace) begin
|
|
writer_stat_fifo_wrport_adr <= (writer_stat_fifo_produce - 1'd1);
|
|
end else begin
|
|
writer_stat_fifo_wrport_adr <= writer_stat_fifo_produce;
|
|
end
|
|
end
|
|
assign writer_stat_fifo_wrport_dat_w = writer_stat_fifo_syncfifo_din;
|
|
assign writer_stat_fifo_wrport_we = (writer_stat_fifo_syncfifo_we & (writer_stat_fifo_syncfifo_writable | writer_stat_fifo_replace));
|
|
assign writer_stat_fifo_do_read = (writer_stat_fifo_syncfifo_readable & writer_stat_fifo_syncfifo_re);
|
|
assign writer_stat_fifo_rdport_adr = writer_stat_fifo_consume;
|
|
assign writer_stat_fifo_syncfifo_dout = writer_stat_fifo_rdport_dat_r;
|
|
assign writer_stat_fifo_syncfifo_writable = (writer_stat_fifo_level != 2'd2);
|
|
assign writer_stat_fifo_syncfifo_readable = (writer_stat_fifo_level != 1'd0);
|
|
always @(*) begin
|
|
subfragments_liteethmacsramwriter_next_state <= 3'd0;
|
|
writer_counter_t_next_value <= 32'd0;
|
|
writer_counter_t_next_value_ce <= 1'd0;
|
|
writer_errors_status_f_next_value <= 32'd0;
|
|
writer_errors_status_f_next_value_ce <= 1'd0;
|
|
writer_slot_ce <= 1'd0;
|
|
writer_start <= 1'd0;
|
|
writer_ongoing <= 1'd0;
|
|
writer_stat_fifo_sink_valid <= 1'd0;
|
|
subfragments_liteethmacsramwriter_next_state <= subfragments_liteethmacsramwriter_state;
|
|
case (subfragments_liteethmacsramwriter_state)
|
|
1'd1: begin
|
|
if (writer_sink_sink_valid) begin
|
|
if ((writer_counter == 11'd1530)) begin
|
|
subfragments_liteethmacsramwriter_next_state <= 2'd3;
|
|
end else begin
|
|
writer_counter_t_next_value <= (writer_counter + writer_inc);
|
|
writer_counter_t_next_value_ce <= 1'd1;
|
|
writer_ongoing <= 1'd1;
|
|
end
|
|
if (writer_sink_sink_last) begin
|
|
if (((writer_sink_sink_payload_error & writer_sink_sink_payload_last_be) != 1'd0)) begin
|
|
subfragments_liteethmacsramwriter_next_state <= 2'd2;
|
|
end else begin
|
|
subfragments_liteethmacsramwriter_next_state <= 3'd4;
|
|
end
|
|
end
|
|
end
|
|
end
|
|
2'd2: begin
|
|
writer_counter_t_next_value <= 1'd0;
|
|
writer_counter_t_next_value_ce <= 1'd1;
|
|
subfragments_liteethmacsramwriter_next_state <= 1'd0;
|
|
end
|
|
2'd3: begin
|
|
if ((writer_sink_sink_valid & writer_sink_sink_last)) begin
|
|
subfragments_liteethmacsramwriter_next_state <= 3'd4;
|
|
end
|
|
end
|
|
3'd4: begin
|
|
writer_counter_t_next_value <= 1'd0;
|
|
writer_counter_t_next_value_ce <= 1'd1;
|
|
writer_slot_ce <= 1'd1;
|
|
writer_stat_fifo_sink_valid <= 1'd1;
|
|
subfragments_liteethmacsramwriter_next_state <= 1'd0;
|
|
end
|
|
default: begin
|
|
if (writer_sink_sink_valid) begin
|
|
if (writer_stat_fifo_sink_ready) begin
|
|
writer_start <= 1'd1;
|
|
writer_ongoing <= 1'd1;
|
|
writer_counter_t_next_value <= (writer_counter + writer_inc);
|
|
writer_counter_t_next_value_ce <= 1'd1;
|
|
subfragments_liteethmacsramwriter_next_state <= 1'd1;
|
|
end else begin
|
|
writer_errors_status_f_next_value <= (writer_errors_status + 1'd1);
|
|
writer_errors_status_f_next_value_ce <= 1'd1;
|
|
subfragments_liteethmacsramwriter_next_state <= 2'd3;
|
|
end
|
|
end
|
|
end
|
|
endcase
|
|
end
|
|
assign reader_cmd_fifo_sink_valid = reader_start_start_re;
|
|
assign reader_cmd_fifo_sink_payload_slot = reader_slot_storage;
|
|
assign reader_cmd_fifo_sink_payload_length = reader_length_storage;
|
|
assign reader_ready_status = reader_cmd_fifo_sink_ready;
|
|
assign reader_level_status = reader_cmd_fifo_level;
|
|
always @(*) begin
|
|
reader_source_source_payload_last_be <= 4'd0;
|
|
if (reader_source_source_last) begin
|
|
case (reader_cmd_fifo_source_payload_length[1:0])
|
|
1'd0: begin
|
|
reader_source_source_payload_last_be <= 4'd8;
|
|
end
|
|
1'd1: begin
|
|
reader_source_source_payload_last_be <= 1'd1;
|
|
end
|
|
2'd2: begin
|
|
reader_source_source_payload_last_be <= 2'd2;
|
|
end
|
|
2'd3: begin
|
|
reader_source_source_payload_last_be <= 3'd4;
|
|
end
|
|
endcase
|
|
end
|
|
end
|
|
assign reader_memory0_adr = reader_read_address[10:2];
|
|
assign reader_memory1_adr = reader_read_address[10:2];
|
|
always @(*) begin
|
|
reader_source_source_payload_data <= 32'd0;
|
|
case (reader_cmd_fifo_source_payload_slot)
|
|
1'd0: begin
|
|
reader_source_source_payload_data <= reader_memory0_dat_r;
|
|
end
|
|
1'd1: begin
|
|
reader_source_source_payload_data <= reader_memory1_dat_r;
|
|
end
|
|
endcase
|
|
end
|
|
assign reader_event00 = reader_eventsourcepulse_status;
|
|
assign reader_event01 = reader_eventsourcepulse_pending;
|
|
always @(*) begin
|
|
reader_eventsourcepulse_clear <= 1'd0;
|
|
if ((reader_pending_re & reader_pending_r)) begin
|
|
reader_eventsourcepulse_clear <= 1'd1;
|
|
end
|
|
end
|
|
assign reader_irq = (reader_pending_status & reader_enable_storage);
|
|
assign reader_eventsourcepulse_status = 1'd0;
|
|
assign reader_cmd_fifo_syncfifo_din = {reader_cmd_fifo_fifo_in_last, reader_cmd_fifo_fifo_in_first, reader_cmd_fifo_fifo_in_payload_length, reader_cmd_fifo_fifo_in_payload_slot};
|
|
assign {reader_cmd_fifo_fifo_out_last, reader_cmd_fifo_fifo_out_first, reader_cmd_fifo_fifo_out_payload_length, reader_cmd_fifo_fifo_out_payload_slot} = reader_cmd_fifo_syncfifo_dout;
|
|
assign reader_cmd_fifo_sink_ready = reader_cmd_fifo_syncfifo_writable;
|
|
assign reader_cmd_fifo_syncfifo_we = reader_cmd_fifo_sink_valid;
|
|
assign reader_cmd_fifo_fifo_in_first = reader_cmd_fifo_sink_first;
|
|
assign reader_cmd_fifo_fifo_in_last = reader_cmd_fifo_sink_last;
|
|
assign reader_cmd_fifo_fifo_in_payload_slot = reader_cmd_fifo_sink_payload_slot;
|
|
assign reader_cmd_fifo_fifo_in_payload_length = reader_cmd_fifo_sink_payload_length;
|
|
assign reader_cmd_fifo_source_valid = reader_cmd_fifo_syncfifo_readable;
|
|
assign reader_cmd_fifo_source_first = reader_cmd_fifo_fifo_out_first;
|
|
assign reader_cmd_fifo_source_last = reader_cmd_fifo_fifo_out_last;
|
|
assign reader_cmd_fifo_source_payload_slot = reader_cmd_fifo_fifo_out_payload_slot;
|
|
assign reader_cmd_fifo_source_payload_length = reader_cmd_fifo_fifo_out_payload_length;
|
|
assign reader_cmd_fifo_syncfifo_re = reader_cmd_fifo_source_ready;
|
|
always @(*) begin
|
|
reader_cmd_fifo_wrport_adr <= 1'd0;
|
|
if (reader_cmd_fifo_replace) begin
|
|
reader_cmd_fifo_wrport_adr <= (reader_cmd_fifo_produce - 1'd1);
|
|
end else begin
|
|
reader_cmd_fifo_wrport_adr <= reader_cmd_fifo_produce;
|
|
end
|
|
end
|
|
assign reader_cmd_fifo_wrport_dat_w = reader_cmd_fifo_syncfifo_din;
|
|
assign reader_cmd_fifo_wrport_we = (reader_cmd_fifo_syncfifo_we & (reader_cmd_fifo_syncfifo_writable | reader_cmd_fifo_replace));
|
|
assign reader_cmd_fifo_do_read = (reader_cmd_fifo_syncfifo_readable & reader_cmd_fifo_syncfifo_re);
|
|
assign reader_cmd_fifo_rdport_adr = reader_cmd_fifo_consume;
|
|
assign reader_cmd_fifo_syncfifo_dout = reader_cmd_fifo_rdport_dat_r;
|
|
assign reader_cmd_fifo_syncfifo_writable = (reader_cmd_fifo_level != 2'd2);
|
|
assign reader_cmd_fifo_syncfifo_readable = (reader_cmd_fifo_level != 1'd0);
|
|
always @(*) begin
|
|
reader_cmd_fifo_source_ready <= 1'd0;
|
|
reader_eventsourcepulse_trigger <= 1'd0;
|
|
subfragments_liteethmacsramreader_next_state <= 2'd0;
|
|
reader_counter_next_value <= 11'd0;
|
|
reader_counter_next_value_ce <= 1'd0;
|
|
reader_source_source_valid <= 1'd0;
|
|
reader_start <= 1'd0;
|
|
reader_source_source_last <= 1'd0;
|
|
reader_read_address <= 11'd0;
|
|
subfragments_liteethmacsramreader_next_state <= subfragments_liteethmacsramreader_state;
|
|
case (subfragments_liteethmacsramreader_state)
|
|
1'd1: begin
|
|
reader_source_source_valid <= 1'd1;
|
|
reader_source_source_last <= (reader_counter >= (reader_cmd_fifo_source_payload_length - 3'd4));
|
|
reader_read_address <= reader_counter;
|
|
if (reader_source_source_ready) begin
|
|
reader_read_address <= (reader_counter + 3'd4);
|
|
reader_counter_next_value <= (reader_counter + 3'd4);
|
|
reader_counter_next_value_ce <= 1'd1;
|
|
if (reader_source_source_last) begin
|
|
subfragments_liteethmacsramreader_next_state <= 2'd2;
|
|
end
|
|
end
|
|
end
|
|
2'd2: begin
|
|
reader_eventsourcepulse_trigger <= 1'd1;
|
|
reader_cmd_fifo_source_ready <= 1'd1;
|
|
subfragments_liteethmacsramreader_next_state <= 1'd0;
|
|
end
|
|
default: begin
|
|
reader_counter_next_value <= 1'd0;
|
|
reader_counter_next_value_ce <= 1'd1;
|
|
if (reader_cmd_fifo_source_valid) begin
|
|
reader_start <= 1'd1;
|
|
subfragments_liteethmacsramreader_next_state <= 1'd1;
|
|
end
|
|
end
|
|
endcase
|
|
end
|
|
assign ev_irq = (writer_irq | reader_irq);
|
|
assign sram0_adr0 = sram0_bus_adr0[8:0];
|
|
assign sram0_bus_dat_r0 = sram0_dat_r0;
|
|
assign sram1_adr0 = sram1_bus_adr0[8:0];
|
|
assign sram1_bus_dat_r0 = sram1_dat_r0;
|
|
always @(*) begin
|
|
sram0_we <= 4'd0;
|
|
sram0_we[0] <= (((sram0_bus_cyc1 & sram0_bus_stb1) & sram0_bus_we1) & sram0_bus_sel1[0]);
|
|
sram0_we[1] <= (((sram0_bus_cyc1 & sram0_bus_stb1) & sram0_bus_we1) & sram0_bus_sel1[1]);
|
|
sram0_we[2] <= (((sram0_bus_cyc1 & sram0_bus_stb1) & sram0_bus_we1) & sram0_bus_sel1[2]);
|
|
sram0_we[3] <= (((sram0_bus_cyc1 & sram0_bus_stb1) & sram0_bus_we1) & sram0_bus_sel1[3]);
|
|
end
|
|
assign sram0_adr1 = sram0_bus_adr1[8:0];
|
|
assign sram0_bus_dat_r1 = sram0_dat_r1;
|
|
assign sram0_dat_w = sram0_bus_dat_w1;
|
|
always @(*) begin
|
|
sram1_we <= 4'd0;
|
|
sram1_we[0] <= (((sram1_bus_cyc1 & sram1_bus_stb1) & sram1_bus_we1) & sram1_bus_sel1[0]);
|
|
sram1_we[1] <= (((sram1_bus_cyc1 & sram1_bus_stb1) & sram1_bus_we1) & sram1_bus_sel1[1]);
|
|
sram1_we[2] <= (((sram1_bus_cyc1 & sram1_bus_stb1) & sram1_bus_we1) & sram1_bus_sel1[2]);
|
|
sram1_we[3] <= (((sram1_bus_cyc1 & sram1_bus_stb1) & sram1_bus_we1) & sram1_bus_sel1[3]);
|
|
end
|
|
assign sram1_adr1 = sram1_bus_adr1[8:0];
|
|
assign sram1_bus_dat_r1 = sram1_dat_r1;
|
|
assign sram1_dat_w = sram1_bus_dat_w1;
|
|
always @(*) begin
|
|
slave_sel <= 4'd0;
|
|
slave_sel[0] <= (bus_adr[10:9] == 1'd0);
|
|
slave_sel[1] <= (bus_adr[10:9] == 1'd1);
|
|
slave_sel[2] <= (bus_adr[10:9] == 2'd2);
|
|
slave_sel[3] <= (bus_adr[10:9] == 2'd3);
|
|
end
|
|
assign sram0_bus_adr0 = bus_adr;
|
|
assign sram0_bus_dat_w0 = bus_dat_w;
|
|
assign sram0_bus_sel0 = bus_sel;
|
|
assign sram0_bus_stb0 = bus_stb;
|
|
assign sram0_bus_we0 = bus_we;
|
|
assign sram0_bus_cti0 = bus_cti;
|
|
assign sram0_bus_bte0 = bus_bte;
|
|
assign sram1_bus_adr0 = bus_adr;
|
|
assign sram1_bus_dat_w0 = bus_dat_w;
|
|
assign sram1_bus_sel0 = bus_sel;
|
|
assign sram1_bus_stb0 = bus_stb;
|
|
assign sram1_bus_we0 = bus_we;
|
|
assign sram1_bus_cti0 = bus_cti;
|
|
assign sram1_bus_bte0 = bus_bte;
|
|
assign sram0_bus_adr1 = bus_adr;
|
|
assign sram0_bus_dat_w1 = bus_dat_w;
|
|
assign sram0_bus_sel1 = bus_sel;
|
|
assign sram0_bus_stb1 = bus_stb;
|
|
assign sram0_bus_we1 = bus_we;
|
|
assign sram0_bus_cti1 = bus_cti;
|
|
assign sram0_bus_bte1 = bus_bte;
|
|
assign sram1_bus_adr1 = bus_adr;
|
|
assign sram1_bus_dat_w1 = bus_dat_w;
|
|
assign sram1_bus_sel1 = bus_sel;
|
|
assign sram1_bus_stb1 = bus_stb;
|
|
assign sram1_bus_we1 = bus_we;
|
|
assign sram1_bus_cti1 = bus_cti;
|
|
assign sram1_bus_bte1 = bus_bte;
|
|
assign sram0_bus_cyc0 = (bus_cyc & slave_sel[0]);
|
|
assign sram1_bus_cyc0 = (bus_cyc & slave_sel[1]);
|
|
assign sram0_bus_cyc1 = (bus_cyc & slave_sel[2]);
|
|
assign sram1_bus_cyc1 = (bus_cyc & slave_sel[3]);
|
|
assign bus_ack = (((sram0_bus_ack0 | sram1_bus_ack0) | sram0_bus_ack1) | sram1_bus_ack1);
|
|
assign bus_err = (((sram0_bus_err0 | sram1_bus_err0) | sram0_bus_err1) | sram1_bus_err1);
|
|
assign bus_dat_r = (((({32{slave_sel_r[0]}} & sram0_bus_dat_r0) | ({32{slave_sel_r[1]}} & sram1_bus_dat_r0)) | ({32{slave_sel_r[2]}} & sram0_bus_dat_r1)) | ({32{slave_sel_r[3]}} & sram1_bus_dat_r1));
|
|
always @(*) begin
|
|
maccore_maccore_we <= 1'd0;
|
|
maccore_maccore_dat_w <= 32'd0;
|
|
maccore_maccore_wishbone_ack <= 1'd0;
|
|
maccore_next_state <= 1'd0;
|
|
maccore_maccore_wishbone_dat_r <= 32'd0;
|
|
maccore_maccore_adr <= 14'd0;
|
|
maccore_next_state <= maccore_state;
|
|
case (maccore_state)
|
|
1'd1: begin
|
|
maccore_maccore_wishbone_ack <= 1'd1;
|
|
maccore_maccore_wishbone_dat_r <= maccore_maccore_dat_r;
|
|
maccore_next_state <= 1'd0;
|
|
end
|
|
default: begin
|
|
maccore_maccore_dat_w <= maccore_maccore_wishbone_dat_w;
|
|
if ((maccore_maccore_wishbone_cyc & maccore_maccore_wishbone_stb)) begin
|
|
maccore_maccore_adr <= maccore_maccore_wishbone_adr;
|
|
maccore_maccore_we <= (maccore_maccore_wishbone_we & (maccore_maccore_wishbone_sel != 1'd0));
|
|
maccore_next_state <= 1'd1;
|
|
end
|
|
end
|
|
endcase
|
|
end
|
|
assign maccore_shared_adr = array_muxed0;
|
|
assign maccore_shared_dat_w = array_muxed1;
|
|
assign maccore_shared_sel = array_muxed2;
|
|
assign maccore_shared_cyc = array_muxed3;
|
|
assign maccore_shared_stb = array_muxed4;
|
|
assign maccore_shared_we = array_muxed5;
|
|
assign maccore_shared_cti = array_muxed6;
|
|
assign maccore_shared_bte = array_muxed7;
|
|
assign wb_bus_dat_r = maccore_shared_dat_r;
|
|
assign wb_bus_ack = (maccore_shared_ack & (maccore_grant == 1'd0));
|
|
assign wb_bus_err = (maccore_shared_err & (maccore_grant == 1'd0));
|
|
assign maccore_request = {wb_bus_cyc};
|
|
assign maccore_grant = 1'd0;
|
|
always @(*) begin
|
|
maccore_slave_sel <= 2'd0;
|
|
maccore_slave_sel[0] <= (maccore_shared_adr[29:11] == 4'd8);
|
|
maccore_slave_sel[1] <= (maccore_shared_adr[29:14] == 1'd0);
|
|
end
|
|
assign bus_adr = maccore_shared_adr;
|
|
assign bus_dat_w = maccore_shared_dat_w;
|
|
assign bus_sel = maccore_shared_sel;
|
|
assign bus_stb = maccore_shared_stb;
|
|
assign bus_we = maccore_shared_we;
|
|
assign bus_cti = maccore_shared_cti;
|
|
assign bus_bte = maccore_shared_bte;
|
|
assign maccore_maccore_wishbone_adr = maccore_shared_adr;
|
|
assign maccore_maccore_wishbone_dat_w = maccore_shared_dat_w;
|
|
assign maccore_maccore_wishbone_sel = maccore_shared_sel;
|
|
assign maccore_maccore_wishbone_stb = maccore_shared_stb;
|
|
assign maccore_maccore_wishbone_we = maccore_shared_we;
|
|
assign maccore_maccore_wishbone_cti = maccore_shared_cti;
|
|
assign maccore_maccore_wishbone_bte = maccore_shared_bte;
|
|
assign bus_cyc = (maccore_shared_cyc & maccore_slave_sel[0]);
|
|
assign maccore_maccore_wishbone_cyc = (maccore_shared_cyc & maccore_slave_sel[1]);
|
|
assign maccore_shared_err = (bus_err | maccore_maccore_wishbone_err);
|
|
assign maccore_wait = ((maccore_shared_stb & maccore_shared_cyc) & (~maccore_shared_ack));
|
|
always @(*) begin
|
|
maccore_error <= 1'd0;
|
|
maccore_shared_dat_r <= 32'd0;
|
|
maccore_shared_ack <= 1'd0;
|
|
maccore_shared_ack <= (bus_ack | maccore_maccore_wishbone_ack);
|
|
maccore_shared_dat_r <= (({32{maccore_slave_sel_r[0]}} & bus_dat_r) | ({32{maccore_slave_sel_r[1]}} & maccore_maccore_wishbone_dat_r));
|
|
if (maccore_done) begin
|
|
maccore_shared_dat_r <= 32'd4294967295;
|
|
maccore_shared_ack <= 1'd1;
|
|
maccore_error <= 1'd1;
|
|
end
|
|
end
|
|
assign maccore_done = (maccore_count == 1'd0);
|
|
assign maccore_csrbank0_sel = (maccore_interface0_bank_bus_adr[13:9] == 1'd0);
|
|
assign maccore_csrbank0_reset0_r = maccore_interface0_bank_bus_dat_w[1:0];
|
|
always @(*) begin
|
|
maccore_csrbank0_reset0_re <= 1'd0;
|
|
maccore_csrbank0_reset0_we <= 1'd0;
|
|
if ((maccore_csrbank0_sel & (maccore_interface0_bank_bus_adr[8:0] == 1'd0))) begin
|
|
maccore_csrbank0_reset0_re <= maccore_interface0_bank_bus_we;
|
|
maccore_csrbank0_reset0_we <= (~maccore_interface0_bank_bus_we);
|
|
end
|
|
end
|
|
assign maccore_csrbank0_scratch0_r = maccore_interface0_bank_bus_dat_w[31:0];
|
|
always @(*) begin
|
|
maccore_csrbank0_scratch0_re <= 1'd0;
|
|
maccore_csrbank0_scratch0_we <= 1'd0;
|
|
if ((maccore_csrbank0_sel & (maccore_interface0_bank_bus_adr[8:0] == 1'd1))) begin
|
|
maccore_csrbank0_scratch0_re <= maccore_interface0_bank_bus_we;
|
|
maccore_csrbank0_scratch0_we <= (~maccore_interface0_bank_bus_we);
|
|
end
|
|
end
|
|
assign maccore_csrbank0_bus_errors_r = maccore_interface0_bank_bus_dat_w[31:0];
|
|
always @(*) begin
|
|
maccore_csrbank0_bus_errors_we <= 1'd0;
|
|
maccore_csrbank0_bus_errors_re <= 1'd0;
|
|
if ((maccore_csrbank0_sel & (maccore_interface0_bank_bus_adr[8:0] == 2'd2))) begin
|
|
maccore_csrbank0_bus_errors_re <= maccore_interface0_bank_bus_we;
|
|
maccore_csrbank0_bus_errors_we <= (~maccore_interface0_bank_bus_we);
|
|
end
|
|
end
|
|
always @(*) begin
|
|
maccore_maccore_soc_rst <= 1'd0;
|
|
if (maccore_maccore_reset_re) begin
|
|
maccore_maccore_soc_rst <= maccore_maccore_reset_storage[0];
|
|
end
|
|
end
|
|
assign maccore_maccore_cpu_rst = maccore_maccore_reset_storage[1];
|
|
assign maccore_csrbank0_reset0_w = maccore_maccore_reset_storage[1:0];
|
|
assign maccore_csrbank0_scratch0_w = maccore_maccore_scratch_storage[31:0];
|
|
assign maccore_csrbank0_bus_errors_w = maccore_maccore_bus_errors_status[31:0];
|
|
assign maccore_maccore_bus_errors_we = maccore_csrbank0_bus_errors_we;
|
|
assign maccore_csrbank1_sel = (maccore_interface1_bank_bus_adr[13:9] == 2'd2);
|
|
assign maccore_csrbank1_sram_writer_slot_r = maccore_interface1_bank_bus_dat_w[0];
|
|
always @(*) begin
|
|
maccore_csrbank1_sram_writer_slot_we <= 1'd0;
|
|
maccore_csrbank1_sram_writer_slot_re <= 1'd0;
|
|
if ((maccore_csrbank1_sel & (maccore_interface1_bank_bus_adr[8:0] == 1'd0))) begin
|
|
maccore_csrbank1_sram_writer_slot_re <= maccore_interface1_bank_bus_we;
|
|
maccore_csrbank1_sram_writer_slot_we <= (~maccore_interface1_bank_bus_we);
|
|
end
|
|
end
|
|
assign maccore_csrbank1_sram_writer_length_r = maccore_interface1_bank_bus_dat_w[31:0];
|
|
always @(*) begin
|
|
maccore_csrbank1_sram_writer_length_we <= 1'd0;
|
|
maccore_csrbank1_sram_writer_length_re <= 1'd0;
|
|
if ((maccore_csrbank1_sel & (maccore_interface1_bank_bus_adr[8:0] == 1'd1))) begin
|
|
maccore_csrbank1_sram_writer_length_re <= maccore_interface1_bank_bus_we;
|
|
maccore_csrbank1_sram_writer_length_we <= (~maccore_interface1_bank_bus_we);
|
|
end
|
|
end
|
|
assign maccore_csrbank1_sram_writer_errors_r = maccore_interface1_bank_bus_dat_w[31:0];
|
|
always @(*) begin
|
|
maccore_csrbank1_sram_writer_errors_re <= 1'd0;
|
|
maccore_csrbank1_sram_writer_errors_we <= 1'd0;
|
|
if ((maccore_csrbank1_sel & (maccore_interface1_bank_bus_adr[8:0] == 2'd2))) begin
|
|
maccore_csrbank1_sram_writer_errors_re <= maccore_interface1_bank_bus_we;
|
|
maccore_csrbank1_sram_writer_errors_we <= (~maccore_interface1_bank_bus_we);
|
|
end
|
|
end
|
|
assign maccore_csrbank1_sram_writer_ev_status_r = maccore_interface1_bank_bus_dat_w[0];
|
|
always @(*) begin
|
|
maccore_csrbank1_sram_writer_ev_status_re <= 1'd0;
|
|
maccore_csrbank1_sram_writer_ev_status_we <= 1'd0;
|
|
if ((maccore_csrbank1_sel & (maccore_interface1_bank_bus_adr[8:0] == 2'd3))) begin
|
|
maccore_csrbank1_sram_writer_ev_status_re <= maccore_interface1_bank_bus_we;
|
|
maccore_csrbank1_sram_writer_ev_status_we <= (~maccore_interface1_bank_bus_we);
|
|
end
|
|
end
|
|
assign maccore_csrbank1_sram_writer_ev_pending_r = maccore_interface1_bank_bus_dat_w[0];
|
|
always @(*) begin
|
|
maccore_csrbank1_sram_writer_ev_pending_we <= 1'd0;
|
|
maccore_csrbank1_sram_writer_ev_pending_re <= 1'd0;
|
|
if ((maccore_csrbank1_sel & (maccore_interface1_bank_bus_adr[8:0] == 3'd4))) begin
|
|
maccore_csrbank1_sram_writer_ev_pending_re <= maccore_interface1_bank_bus_we;
|
|
maccore_csrbank1_sram_writer_ev_pending_we <= (~maccore_interface1_bank_bus_we);
|
|
end
|
|
end
|
|
assign maccore_csrbank1_sram_writer_ev_enable0_r = maccore_interface1_bank_bus_dat_w[0];
|
|
always @(*) begin
|
|
maccore_csrbank1_sram_writer_ev_enable0_we <= 1'd0;
|
|
maccore_csrbank1_sram_writer_ev_enable0_re <= 1'd0;
|
|
if ((maccore_csrbank1_sel & (maccore_interface1_bank_bus_adr[8:0] == 3'd5))) begin
|
|
maccore_csrbank1_sram_writer_ev_enable0_re <= maccore_interface1_bank_bus_we;
|
|
maccore_csrbank1_sram_writer_ev_enable0_we <= (~maccore_interface1_bank_bus_we);
|
|
end
|
|
end
|
|
assign reader_start_start_r = maccore_interface1_bank_bus_dat_w[0];
|
|
always @(*) begin
|
|
reader_start_start_re <= 1'd0;
|
|
reader_start_start_we <= 1'd0;
|
|
if ((maccore_csrbank1_sel & (maccore_interface1_bank_bus_adr[8:0] == 3'd6))) begin
|
|
reader_start_start_re <= maccore_interface1_bank_bus_we;
|
|
reader_start_start_we <= (~maccore_interface1_bank_bus_we);
|
|
end
|
|
end
|
|
assign maccore_csrbank1_sram_reader_ready_r = maccore_interface1_bank_bus_dat_w[0];
|
|
always @(*) begin
|
|
maccore_csrbank1_sram_reader_ready_re <= 1'd0;
|
|
maccore_csrbank1_sram_reader_ready_we <= 1'd0;
|
|
if ((maccore_csrbank1_sel & (maccore_interface1_bank_bus_adr[8:0] == 3'd7))) begin
|
|
maccore_csrbank1_sram_reader_ready_re <= maccore_interface1_bank_bus_we;
|
|
maccore_csrbank1_sram_reader_ready_we <= (~maccore_interface1_bank_bus_we);
|
|
end
|
|
end
|
|
assign maccore_csrbank1_sram_reader_level_r = maccore_interface1_bank_bus_dat_w[1:0];
|
|
always @(*) begin
|
|
maccore_csrbank1_sram_reader_level_we <= 1'd0;
|
|
maccore_csrbank1_sram_reader_level_re <= 1'd0;
|
|
if ((maccore_csrbank1_sel & (maccore_interface1_bank_bus_adr[8:0] == 4'd8))) begin
|
|
maccore_csrbank1_sram_reader_level_re <= maccore_interface1_bank_bus_we;
|
|
maccore_csrbank1_sram_reader_level_we <= (~maccore_interface1_bank_bus_we);
|
|
end
|
|
end
|
|
assign maccore_csrbank1_sram_reader_slot0_r = maccore_interface1_bank_bus_dat_w[0];
|
|
always @(*) begin
|
|
maccore_csrbank1_sram_reader_slot0_we <= 1'd0;
|
|
maccore_csrbank1_sram_reader_slot0_re <= 1'd0;
|
|
if ((maccore_csrbank1_sel & (maccore_interface1_bank_bus_adr[8:0] == 4'd9))) begin
|
|
maccore_csrbank1_sram_reader_slot0_re <= maccore_interface1_bank_bus_we;
|
|
maccore_csrbank1_sram_reader_slot0_we <= (~maccore_interface1_bank_bus_we);
|
|
end
|
|
end
|
|
assign maccore_csrbank1_sram_reader_length0_r = maccore_interface1_bank_bus_dat_w[10:0];
|
|
always @(*) begin
|
|
maccore_csrbank1_sram_reader_length0_re <= 1'd0;
|
|
maccore_csrbank1_sram_reader_length0_we <= 1'd0;
|
|
if ((maccore_csrbank1_sel & (maccore_interface1_bank_bus_adr[8:0] == 4'd10))) begin
|
|
maccore_csrbank1_sram_reader_length0_re <= maccore_interface1_bank_bus_we;
|
|
maccore_csrbank1_sram_reader_length0_we <= (~maccore_interface1_bank_bus_we);
|
|
end
|
|
end
|
|
assign maccore_csrbank1_sram_reader_ev_status_r = maccore_interface1_bank_bus_dat_w[0];
|
|
always @(*) begin
|
|
maccore_csrbank1_sram_reader_ev_status_we <= 1'd0;
|
|
maccore_csrbank1_sram_reader_ev_status_re <= 1'd0;
|
|
if ((maccore_csrbank1_sel & (maccore_interface1_bank_bus_adr[8:0] == 4'd11))) begin
|
|
maccore_csrbank1_sram_reader_ev_status_re <= maccore_interface1_bank_bus_we;
|
|
maccore_csrbank1_sram_reader_ev_status_we <= (~maccore_interface1_bank_bus_we);
|
|
end
|
|
end
|
|
assign maccore_csrbank1_sram_reader_ev_pending_r = maccore_interface1_bank_bus_dat_w[0];
|
|
always @(*) begin
|
|
maccore_csrbank1_sram_reader_ev_pending_we <= 1'd0;
|
|
maccore_csrbank1_sram_reader_ev_pending_re <= 1'd0;
|
|
if ((maccore_csrbank1_sel & (maccore_interface1_bank_bus_adr[8:0] == 4'd12))) begin
|
|
maccore_csrbank1_sram_reader_ev_pending_re <= maccore_interface1_bank_bus_we;
|
|
maccore_csrbank1_sram_reader_ev_pending_we <= (~maccore_interface1_bank_bus_we);
|
|
end
|
|
end
|
|
assign maccore_csrbank1_sram_reader_ev_enable0_r = maccore_interface1_bank_bus_dat_w[0];
|
|
always @(*) begin
|
|
maccore_csrbank1_sram_reader_ev_enable0_re <= 1'd0;
|
|
maccore_csrbank1_sram_reader_ev_enable0_we <= 1'd0;
|
|
if ((maccore_csrbank1_sel & (maccore_interface1_bank_bus_adr[8:0] == 4'd13))) begin
|
|
maccore_csrbank1_sram_reader_ev_enable0_re <= maccore_interface1_bank_bus_we;
|
|
maccore_csrbank1_sram_reader_ev_enable0_we <= (~maccore_interface1_bank_bus_we);
|
|
end
|
|
end
|
|
assign maccore_csrbank1_preamble_crc_r = maccore_interface1_bank_bus_dat_w[0];
|
|
always @(*) begin
|
|
maccore_csrbank1_preamble_crc_we <= 1'd0;
|
|
maccore_csrbank1_preamble_crc_re <= 1'd0;
|
|
if ((maccore_csrbank1_sel & (maccore_interface1_bank_bus_adr[8:0] == 4'd14))) begin
|
|
maccore_csrbank1_preamble_crc_re <= maccore_interface1_bank_bus_we;
|
|
maccore_csrbank1_preamble_crc_we <= (~maccore_interface1_bank_bus_we);
|
|
end
|
|
end
|
|
assign maccore_csrbank1_preamble_errors_r = maccore_interface1_bank_bus_dat_w[31:0];
|
|
always @(*) begin
|
|
maccore_csrbank1_preamble_errors_we <= 1'd0;
|
|
maccore_csrbank1_preamble_errors_re <= 1'd0;
|
|
if ((maccore_csrbank1_sel & (maccore_interface1_bank_bus_adr[8:0] == 4'd15))) begin
|
|
maccore_csrbank1_preamble_errors_re <= maccore_interface1_bank_bus_we;
|
|
maccore_csrbank1_preamble_errors_we <= (~maccore_interface1_bank_bus_we);
|
|
end
|
|
end
|
|
assign maccore_csrbank1_crc_errors_r = maccore_interface1_bank_bus_dat_w[31:0];
|
|
always @(*) begin
|
|
maccore_csrbank1_crc_errors_re <= 1'd0;
|
|
maccore_csrbank1_crc_errors_we <= 1'd0;
|
|
if ((maccore_csrbank1_sel & (maccore_interface1_bank_bus_adr[8:0] == 5'd16))) begin
|
|
maccore_csrbank1_crc_errors_re <= maccore_interface1_bank_bus_we;
|
|
maccore_csrbank1_crc_errors_we <= (~maccore_interface1_bank_bus_we);
|
|
end
|
|
end
|
|
assign maccore_csrbank1_sram_writer_slot_w = writer_slot_status;
|
|
assign writer_slot_we = maccore_csrbank1_sram_writer_slot_we;
|
|
assign maccore_csrbank1_sram_writer_length_w = writer_length_status[31:0];
|
|
assign writer_length_we = maccore_csrbank1_sram_writer_length_we;
|
|
assign maccore_csrbank1_sram_writer_errors_w = writer_errors_status[31:0];
|
|
assign writer_errors_we = maccore_csrbank1_sram_writer_errors_we;
|
|
assign writer_status_status = writer_available0;
|
|
assign maccore_csrbank1_sram_writer_ev_status_w = writer_status_status;
|
|
assign writer_status_we = maccore_csrbank1_sram_writer_ev_status_we;
|
|
assign writer_pending_status = writer_available1;
|
|
assign maccore_csrbank1_sram_writer_ev_pending_w = writer_pending_status;
|
|
assign writer_pending_we = maccore_csrbank1_sram_writer_ev_pending_we;
|
|
assign writer_available2 = writer_enable_storage;
|
|
assign maccore_csrbank1_sram_writer_ev_enable0_w = writer_enable_storage;
|
|
assign maccore_csrbank1_sram_reader_ready_w = reader_ready_status;
|
|
assign reader_ready_we = maccore_csrbank1_sram_reader_ready_we;
|
|
assign maccore_csrbank1_sram_reader_level_w = reader_level_status[1:0];
|
|
assign reader_level_we = maccore_csrbank1_sram_reader_level_we;
|
|
assign maccore_csrbank1_sram_reader_slot0_w = reader_slot_storage;
|
|
assign maccore_csrbank1_sram_reader_length0_w = reader_length_storage[10:0];
|
|
assign reader_status_status = reader_event00;
|
|
assign maccore_csrbank1_sram_reader_ev_status_w = reader_status_status;
|
|
assign reader_status_we = maccore_csrbank1_sram_reader_ev_status_we;
|
|
assign reader_pending_status = reader_event01;
|
|
assign maccore_csrbank1_sram_reader_ev_pending_w = reader_pending_status;
|
|
assign reader_pending_we = maccore_csrbank1_sram_reader_ev_pending_we;
|
|
assign reader_event02 = reader_enable_storage;
|
|
assign maccore_csrbank1_sram_reader_ev_enable0_w = reader_enable_storage;
|
|
assign maccore_csrbank1_preamble_crc_w = preamble_crc_status;
|
|
assign preamble_crc_we = maccore_csrbank1_preamble_crc_we;
|
|
assign maccore_csrbank1_preamble_errors_w = preamble_errors_status[31:0];
|
|
assign preamble_errors_we = maccore_csrbank1_preamble_errors_we;
|
|
assign maccore_csrbank1_crc_errors_w = crc_errors_status[31:0];
|
|
assign crc_errors_we = maccore_csrbank1_crc_errors_we;
|
|
assign maccore_csrbank2_sel = (maccore_interface2_bank_bus_adr[13:9] == 1'd1);
|
|
assign maccore_csrbank2_mode_detection_mode_r = maccore_interface2_bank_bus_dat_w[0];
|
|
always @(*) begin
|
|
maccore_csrbank2_mode_detection_mode_re <= 1'd0;
|
|
maccore_csrbank2_mode_detection_mode_we <= 1'd0;
|
|
if ((maccore_csrbank2_sel & (maccore_interface2_bank_bus_adr[8:0] == 1'd0))) begin
|
|
maccore_csrbank2_mode_detection_mode_re <= maccore_interface2_bank_bus_we;
|
|
maccore_csrbank2_mode_detection_mode_we <= (~maccore_interface2_bank_bus_we);
|
|
end
|
|
end
|
|
assign maccore_csrbank2_crg_reset0_r = maccore_interface2_bank_bus_dat_w[0];
|
|
always @(*) begin
|
|
maccore_csrbank2_crg_reset0_re <= 1'd0;
|
|
maccore_csrbank2_crg_reset0_we <= 1'd0;
|
|
if ((maccore_csrbank2_sel & (maccore_interface2_bank_bus_adr[8:0] == 1'd1))) begin
|
|
maccore_csrbank2_crg_reset0_re <= maccore_interface2_bank_bus_we;
|
|
maccore_csrbank2_crg_reset0_we <= (~maccore_interface2_bank_bus_we);
|
|
end
|
|
end
|
|
assign maccore_csrbank2_mdio_w0_r = maccore_interface2_bank_bus_dat_w[2:0];
|
|
always @(*) begin
|
|
maccore_csrbank2_mdio_w0_we <= 1'd0;
|
|
maccore_csrbank2_mdio_w0_re <= 1'd0;
|
|
if ((maccore_csrbank2_sel & (maccore_interface2_bank_bus_adr[8:0] == 2'd2))) begin
|
|
maccore_csrbank2_mdio_w0_re <= maccore_interface2_bank_bus_we;
|
|
maccore_csrbank2_mdio_w0_we <= (~maccore_interface2_bank_bus_we);
|
|
end
|
|
end
|
|
assign maccore_csrbank2_mdio_r_r = maccore_interface2_bank_bus_dat_w[0];
|
|
always @(*) begin
|
|
maccore_csrbank2_mdio_r_re <= 1'd0;
|
|
maccore_csrbank2_mdio_r_we <= 1'd0;
|
|
if ((maccore_csrbank2_sel & (maccore_interface2_bank_bus_adr[8:0] == 2'd3))) begin
|
|
maccore_csrbank2_mdio_r_re <= maccore_interface2_bank_bus_we;
|
|
maccore_csrbank2_mdio_r_we <= (~maccore_interface2_bank_bus_we);
|
|
end
|
|
end
|
|
assign maccore_csrbank2_mode_detection_mode_w = maccore_ethphy_mode_status;
|
|
assign maccore_ethphy_mode_we = maccore_csrbank2_mode_detection_mode_we;
|
|
assign maccore_csrbank2_crg_reset0_w = maccore_ethphy_reset_storage;
|
|
assign maccore_ethphy_mdc = maccore_ethphy__w_storage[0];
|
|
assign maccore_ethphy_oe = maccore_ethphy__w_storage[1];
|
|
assign maccore_ethphy_w = maccore_ethphy__w_storage[2];
|
|
assign maccore_csrbank2_mdio_w0_w = maccore_ethphy__w_storage[2:0];
|
|
assign maccore_csrbank2_mdio_r_w = maccore_ethphy__r_status;
|
|
assign maccore_ethphy__r_we = maccore_csrbank2_mdio_r_we;
|
|
assign maccore_csr_interconnect_adr = maccore_maccore_adr;
|
|
assign maccore_csr_interconnect_we = maccore_maccore_we;
|
|
assign maccore_csr_interconnect_dat_w = maccore_maccore_dat_w;
|
|
assign maccore_maccore_dat_r = maccore_csr_interconnect_dat_r;
|
|
assign maccore_interface0_bank_bus_adr = maccore_csr_interconnect_adr;
|
|
assign maccore_interface1_bank_bus_adr = maccore_csr_interconnect_adr;
|
|
assign maccore_interface2_bank_bus_adr = maccore_csr_interconnect_adr;
|
|
assign maccore_interface0_bank_bus_we = maccore_csr_interconnect_we;
|
|
assign maccore_interface1_bank_bus_we = maccore_csr_interconnect_we;
|
|
assign maccore_interface2_bank_bus_we = maccore_csr_interconnect_we;
|
|
assign maccore_interface0_bank_bus_dat_w = maccore_csr_interconnect_dat_w;
|
|
assign maccore_interface1_bank_bus_dat_w = maccore_csr_interconnect_dat_w;
|
|
assign maccore_interface2_bank_bus_dat_w = maccore_csr_interconnect_dat_w;
|
|
assign maccore_csr_interconnect_dat_r = ((maccore_interface0_bank_bus_dat_r | maccore_interface1_bank_bus_dat_r) | maccore_interface2_bank_bus_dat_r);
|
|
always @(*) begin
|
|
array_muxed0 <= 30'd0;
|
|
case (maccore_grant)
|
|
default: begin
|
|
array_muxed0 <= wb_bus_adr;
|
|
end
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
array_muxed1 <= 32'd0;
|
|
case (maccore_grant)
|
|
default: begin
|
|
array_muxed1 <= wb_bus_dat_w;
|
|
end
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
array_muxed2 <= 4'd0;
|
|
case (maccore_grant)
|
|
default: begin
|
|
array_muxed2 <= wb_bus_sel;
|
|
end
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
array_muxed3 <= 1'd0;
|
|
case (maccore_grant)
|
|
default: begin
|
|
array_muxed3 <= wb_bus_cyc;
|
|
end
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
array_muxed4 <= 1'd0;
|
|
case (maccore_grant)
|
|
default: begin
|
|
array_muxed4 <= wb_bus_stb;
|
|
end
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
array_muxed5 <= 1'd0;
|
|
case (maccore_grant)
|
|
default: begin
|
|
array_muxed5 <= wb_bus_we;
|
|
end
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
array_muxed6 <= 3'd0;
|
|
case (maccore_grant)
|
|
default: begin
|
|
array_muxed6 <= wb_bus_cti;
|
|
end
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
array_muxed7 <= 2'd0;
|
|
case (maccore_grant)
|
|
default: begin
|
|
array_muxed7 <= wb_bus_bte;
|
|
end
|
|
endcase
|
|
end
|
|
assign maccore_ethphy_toggle_o = xilinxmultiregimpl0_regs1;
|
|
always @(*) begin
|
|
maccore_ethphy__r_status <= 1'd0;
|
|
maccore_ethphy__r_status <= maccore_ethphy_r;
|
|
maccore_ethphy__r_status <= xilinxmultiregimpl1_regs1;
|
|
end
|
|
assign ps_preamble_error_toggle_o = xilinxmultiregimpl2_regs1;
|
|
assign ps_crc_error_toggle_o = xilinxmultiregimpl3_regs1;
|
|
assign tx_cdc_cdc_produce_rdomain = xilinxmultiregimpl4_regs1;
|
|
assign tx_cdc_cdc_consume_wdomain = xilinxmultiregimpl5_regs1;
|
|
assign rx_cdc_cdc_produce_rdomain = xilinxmultiregimpl6_regs1;
|
|
assign rx_cdc_cdc_consume_wdomain = xilinxmultiregimpl7_regs1;
|
|
|
|
always @(posedge eth_rx_clk) begin
|
|
maccore_ethphy_eth_counter <= (maccore_ethphy_eth_counter + 1'd1);
|
|
if (maccore_ethphy_i) begin
|
|
maccore_ethphy_toggle_i <= (~maccore_ethphy_toggle_i);
|
|
end
|
|
maccore_ethphy_liteethphygmiimiirx_pads_d_rx_dv <= gmii_eth_rx_dv;
|
|
maccore_ethphy_liteethphygmiimiirx_pads_d_rx_data <= gmii_eth_rx_data;
|
|
maccore_ethphy_liteethphygmiimiirx_gmii_rx_dv_d <= maccore_ethphy_liteethphygmiimiirx_pads_d_rx_dv;
|
|
maccore_ethphy_liteethphygmiimiirx_gmii_rx_source_valid <= maccore_ethphy_liteethphygmiimiirx_pads_d_rx_dv;
|
|
maccore_ethphy_liteethphygmiimiirx_gmii_rx_source_payload_data <= maccore_ethphy_liteethphygmiimiirx_pads_d_rx_data;
|
|
maccore_ethphy_liteethphygmiimiirx_converter_reset <= (~maccore_ethphy_liteethphygmiimiirx_pads_d_rx_dv);
|
|
maccore_ethphy_liteethphygmiimiirx_converter_sink_valid <= 1'd1;
|
|
maccore_ethphy_liteethphygmiimiirx_converter_sink_payload_data <= maccore_ethphy_liteethphygmiimiirx_pads_d_rx_data;
|
|
if (maccore_ethphy_liteethphygmiimiirx_converter_converter_source_ready) begin
|
|
maccore_ethphy_liteethphygmiimiirx_converter_converter_strobe_all <= 1'd0;
|
|
end
|
|
if (maccore_ethphy_liteethphygmiimiirx_converter_converter_load_part) begin
|
|
if (((maccore_ethphy_liteethphygmiimiirx_converter_converter_demux == 1'd1) | maccore_ethphy_liteethphygmiimiirx_converter_converter_sink_last)) begin
|
|
maccore_ethphy_liteethphygmiimiirx_converter_converter_demux <= 1'd0;
|
|
maccore_ethphy_liteethphygmiimiirx_converter_converter_strobe_all <= 1'd1;
|
|
end else begin
|
|
maccore_ethphy_liteethphygmiimiirx_converter_converter_demux <= (maccore_ethphy_liteethphygmiimiirx_converter_converter_demux + 1'd1);
|
|
end
|
|
end
|
|
if ((maccore_ethphy_liteethphygmiimiirx_converter_converter_source_valid & maccore_ethphy_liteethphygmiimiirx_converter_converter_source_ready)) begin
|
|
if ((maccore_ethphy_liteethphygmiimiirx_converter_converter_sink_valid & maccore_ethphy_liteethphygmiimiirx_converter_converter_sink_ready)) begin
|
|
maccore_ethphy_liteethphygmiimiirx_converter_converter_source_first <= maccore_ethphy_liteethphygmiimiirx_converter_converter_sink_first;
|
|
maccore_ethphy_liteethphygmiimiirx_converter_converter_source_last <= maccore_ethphy_liteethphygmiimiirx_converter_converter_sink_last;
|
|
end else begin
|
|
maccore_ethphy_liteethphygmiimiirx_converter_converter_source_first <= 1'd0;
|
|
maccore_ethphy_liteethphygmiimiirx_converter_converter_source_last <= 1'd0;
|
|
end
|
|
end else begin
|
|
if ((maccore_ethphy_liteethphygmiimiirx_converter_converter_sink_valid & maccore_ethphy_liteethphygmiimiirx_converter_converter_sink_ready)) begin
|
|
maccore_ethphy_liteethphygmiimiirx_converter_converter_source_first <= (maccore_ethphy_liteethphygmiimiirx_converter_converter_sink_first | maccore_ethphy_liteethphygmiimiirx_converter_converter_source_first);
|
|
maccore_ethphy_liteethphygmiimiirx_converter_converter_source_last <= (maccore_ethphy_liteethphygmiimiirx_converter_converter_sink_last | maccore_ethphy_liteethphygmiimiirx_converter_converter_source_last);
|
|
end
|
|
end
|
|
if (maccore_ethphy_liteethphygmiimiirx_converter_converter_load_part) begin
|
|
case (maccore_ethphy_liteethphygmiimiirx_converter_converter_demux)
|
|
1'd0: begin
|
|
maccore_ethphy_liteethphygmiimiirx_converter_converter_source_payload_data[3:0] <= maccore_ethphy_liteethphygmiimiirx_converter_converter_sink_payload_data;
|
|
end
|
|
1'd1: begin
|
|
maccore_ethphy_liteethphygmiimiirx_converter_converter_source_payload_data[7:4] <= maccore_ethphy_liteethphygmiimiirx_converter_converter_sink_payload_data;
|
|
end
|
|
endcase
|
|
end
|
|
if (maccore_ethphy_liteethphygmiimiirx_converter_converter_load_part) begin
|
|
maccore_ethphy_liteethphygmiimiirx_converter_converter_source_payload_valid_token_count <= (maccore_ethphy_liteethphygmiimiirx_converter_converter_demux + 1'd1);
|
|
end
|
|
if (maccore_ethphy_liteethphygmiimiirx_converter_reset) begin
|
|
maccore_ethphy_liteethphygmiimiirx_converter_converter_source_payload_data <= 8'd0;
|
|
maccore_ethphy_liteethphygmiimiirx_converter_converter_source_payload_valid_token_count <= 2'd0;
|
|
maccore_ethphy_liteethphygmiimiirx_converter_converter_demux <= 1'd0;
|
|
maccore_ethphy_liteethphygmiimiirx_converter_converter_strobe_all <= 1'd0;
|
|
end
|
|
subfragments_liteethmacpreamblechecker_state <= subfragments_liteethmacpreamblechecker_next_state;
|
|
if (liteethmaccrc32checker_crc_ce) begin
|
|
liteethmaccrc32checker_crc_reg <= liteethmaccrc32checker_crc_next;
|
|
end
|
|
if (liteethmaccrc32checker_crc_reset) begin
|
|
liteethmaccrc32checker_crc_reg <= 32'd4294967295;
|
|
end
|
|
if (((liteethmaccrc32checker_syncfifo_syncfifo_we & liteethmaccrc32checker_syncfifo_syncfifo_writable) & (~liteethmaccrc32checker_syncfifo_replace))) begin
|
|
if ((liteethmaccrc32checker_syncfifo_produce == 3'd4)) begin
|
|
liteethmaccrc32checker_syncfifo_produce <= 1'd0;
|
|
end else begin
|
|
liteethmaccrc32checker_syncfifo_produce <= (liteethmaccrc32checker_syncfifo_produce + 1'd1);
|
|
end
|
|
end
|
|
if (liteethmaccrc32checker_syncfifo_do_read) begin
|
|
if ((liteethmaccrc32checker_syncfifo_consume == 3'd4)) begin
|
|
liteethmaccrc32checker_syncfifo_consume <= 1'd0;
|
|
end else begin
|
|
liteethmaccrc32checker_syncfifo_consume <= (liteethmaccrc32checker_syncfifo_consume + 1'd1);
|
|
end
|
|
end
|
|
if (((liteethmaccrc32checker_syncfifo_syncfifo_we & liteethmaccrc32checker_syncfifo_syncfifo_writable) & (~liteethmaccrc32checker_syncfifo_replace))) begin
|
|
if ((~liteethmaccrc32checker_syncfifo_do_read)) begin
|
|
liteethmaccrc32checker_syncfifo_level <= (liteethmaccrc32checker_syncfifo_level + 1'd1);
|
|
end
|
|
end else begin
|
|
if (liteethmaccrc32checker_syncfifo_do_read) begin
|
|
liteethmaccrc32checker_syncfifo_level <= (liteethmaccrc32checker_syncfifo_level - 1'd1);
|
|
end
|
|
end
|
|
if (liteethmaccrc32checker_fifo_reset) begin
|
|
liteethmaccrc32checker_syncfifo_level <= 3'd0;
|
|
liteethmaccrc32checker_syncfifo_produce <= 3'd0;
|
|
liteethmaccrc32checker_syncfifo_consume <= 3'd0;
|
|
end
|
|
subfragments_liteethmaccrc32checker_state <= subfragments_liteethmaccrc32checker_next_state;
|
|
if (((~crc32_checker_source_valid) | crc32_checker_source_ready)) begin
|
|
crc32_checker_source_valid <= crc32_checker_sink_valid;
|
|
crc32_checker_source_first <= crc32_checker_sink_first;
|
|
crc32_checker_source_last <= crc32_checker_sink_last;
|
|
crc32_checker_source_payload_data <= crc32_checker_sink_payload_data;
|
|
crc32_checker_source_payload_last_be <= crc32_checker_sink_payload_last_be;
|
|
crc32_checker_source_payload_error <= crc32_checker_sink_payload_error;
|
|
end
|
|
if (ps_preamble_error_i) begin
|
|
ps_preamble_error_toggle_i <= (~ps_preamble_error_toggle_i);
|
|
end
|
|
if (ps_crc_error_i) begin
|
|
ps_crc_error_toggle_i <= (~ps_crc_error_toggle_i);
|
|
end
|
|
if (rx_converter_converter_source_ready) begin
|
|
rx_converter_converter_strobe_all <= 1'd0;
|
|
end
|
|
if (rx_converter_converter_load_part) begin
|
|
if (((rx_converter_converter_demux == 2'd3) | rx_converter_converter_sink_last)) begin
|
|
rx_converter_converter_demux <= 1'd0;
|
|
rx_converter_converter_strobe_all <= 1'd1;
|
|
end else begin
|
|
rx_converter_converter_demux <= (rx_converter_converter_demux + 1'd1);
|
|
end
|
|
end
|
|
if ((rx_converter_converter_source_valid & rx_converter_converter_source_ready)) begin
|
|
if ((rx_converter_converter_sink_valid & rx_converter_converter_sink_ready)) begin
|
|
rx_converter_converter_source_first <= rx_converter_converter_sink_first;
|
|
rx_converter_converter_source_last <= rx_converter_converter_sink_last;
|
|
end else begin
|
|
rx_converter_converter_source_first <= 1'd0;
|
|
rx_converter_converter_source_last <= 1'd0;
|
|
end
|
|
end else begin
|
|
if ((rx_converter_converter_sink_valid & rx_converter_converter_sink_ready)) begin
|
|
rx_converter_converter_source_first <= (rx_converter_converter_sink_first | rx_converter_converter_source_first);
|
|
rx_converter_converter_source_last <= (rx_converter_converter_sink_last | rx_converter_converter_source_last);
|
|
end
|
|
end
|
|
if (rx_converter_converter_load_part) begin
|
|
case (rx_converter_converter_demux)
|
|
1'd0: begin
|
|
rx_converter_converter_source_payload_data[9:0] <= rx_converter_converter_sink_payload_data;
|
|
end
|
|
1'd1: begin
|
|
rx_converter_converter_source_payload_data[19:10] <= rx_converter_converter_sink_payload_data;
|
|
end
|
|
2'd2: begin
|
|
rx_converter_converter_source_payload_data[29:20] <= rx_converter_converter_sink_payload_data;
|
|
end
|
|
2'd3: begin
|
|
rx_converter_converter_source_payload_data[39:30] <= rx_converter_converter_sink_payload_data;
|
|
end
|
|
endcase
|
|
end
|
|
if (rx_converter_converter_load_part) begin
|
|
rx_converter_converter_source_payload_valid_token_count <= (rx_converter_converter_demux + 1'd1);
|
|
end
|
|
rx_cdc_cdc_graycounter0_q_binary <= rx_cdc_cdc_graycounter0_q_next_binary;
|
|
rx_cdc_cdc_graycounter0_q <= rx_cdc_cdc_graycounter0_q_next;
|
|
if (eth_rx_rst) begin
|
|
maccore_ethphy_liteethphygmiimiirx_gmii_rx_source_valid <= 1'd0;
|
|
maccore_ethphy_liteethphygmiimiirx_gmii_rx_source_payload_data <= 8'd0;
|
|
maccore_ethphy_liteethphygmiimiirx_gmii_rx_dv_d <= 1'd0;
|
|
maccore_ethphy_liteethphygmiimiirx_converter_sink_valid <= 1'd0;
|
|
maccore_ethphy_liteethphygmiimiirx_converter_sink_payload_data <= 4'd0;
|
|
maccore_ethphy_liteethphygmiimiirx_converter_converter_source_payload_data <= 8'd0;
|
|
maccore_ethphy_liteethphygmiimiirx_converter_converter_source_payload_valid_token_count <= 2'd0;
|
|
maccore_ethphy_liteethphygmiimiirx_converter_converter_demux <= 1'd0;
|
|
maccore_ethphy_liteethphygmiimiirx_converter_converter_strobe_all <= 1'd0;
|
|
maccore_ethphy_liteethphygmiimiirx_converter_reset <= 1'd0;
|
|
liteethmaccrc32checker_crc_reg <= 32'd4294967295;
|
|
liteethmaccrc32checker_syncfifo_level <= 3'd0;
|
|
liteethmaccrc32checker_syncfifo_produce <= 3'd0;
|
|
liteethmaccrc32checker_syncfifo_consume <= 3'd0;
|
|
crc32_checker_source_valid <= 1'd0;
|
|
crc32_checker_source_payload_data <= 8'd0;
|
|
crc32_checker_source_payload_last_be <= 1'd0;
|
|
crc32_checker_source_payload_error <= 1'd0;
|
|
rx_converter_converter_source_payload_data <= 40'd0;
|
|
rx_converter_converter_source_payload_valid_token_count <= 3'd0;
|
|
rx_converter_converter_demux <= 2'd0;
|
|
rx_converter_converter_strobe_all <= 1'd0;
|
|
rx_cdc_cdc_graycounter0_q <= 6'd0;
|
|
rx_cdc_cdc_graycounter0_q_binary <= 6'd0;
|
|
subfragments_liteethmacpreamblechecker_state <= 1'd0;
|
|
subfragments_liteethmaccrc32checker_state <= 2'd0;
|
|
end
|
|
xilinxmultiregimpl7_regs0 <= rx_cdc_cdc_graycounter1_q;
|
|
xilinxmultiregimpl7_regs1 <= xilinxmultiregimpl7_regs0;
|
|
end
|
|
|
|
always @(posedge eth_tx_clk) begin
|
|
if ((maccore_ethphy_mode0 == 1'd1)) begin
|
|
gmii_eth_tx_en <= maccore_ethphy_liteethphygmiimiitx_mii_tx_pads_tx_en;
|
|
gmii_eth_tx_data <= maccore_ethphy_liteethphygmiimiitx_mii_tx_pads_tx_data;
|
|
end else begin
|
|
gmii_eth_tx_en <= maccore_ethphy_liteethphygmiimiitx_gmii_tx_pads_tx_en;
|
|
gmii_eth_tx_data <= maccore_ethphy_liteethphygmiimiitx_gmii_tx_pads_tx_data;
|
|
end
|
|
maccore_ethphy_liteethphygmiimiitx_gmii_tx_pads_tx_er <= 1'd0;
|
|
maccore_ethphy_liteethphygmiimiitx_gmii_tx_pads_tx_en <= maccore_ethphy_liteethphygmiimiitx_gmii_tx_sink_valid;
|
|
maccore_ethphy_liteethphygmiimiitx_gmii_tx_pads_tx_data <= maccore_ethphy_liteethphygmiimiitx_gmii_tx_sink_payload_data;
|
|
maccore_ethphy_liteethphygmiimiitx_gmii_tx_sink_ready <= 1'd1;
|
|
maccore_ethphy_liteethphygmiimiitx_mii_tx_pads_tx_er <= 1'd0;
|
|
maccore_ethphy_liteethphygmiimiitx_mii_tx_pads_tx_en <= maccore_ethphy_liteethphygmiimiitx_converter_source_valid;
|
|
maccore_ethphy_liteethphygmiimiitx_mii_tx_pads_tx_data <= maccore_ethphy_liteethphygmiimiitx_converter_source_payload_data;
|
|
if ((maccore_ethphy_liteethphygmiimiitx_converter_converter_source_valid & maccore_ethphy_liteethphygmiimiitx_converter_converter_source_ready)) begin
|
|
if (maccore_ethphy_liteethphygmiimiitx_converter_converter_last) begin
|
|
maccore_ethphy_liteethphygmiimiitx_converter_converter_mux <= 1'd0;
|
|
end else begin
|
|
maccore_ethphy_liteethphygmiimiitx_converter_converter_mux <= (maccore_ethphy_liteethphygmiimiitx_converter_converter_mux + 1'd1);
|
|
end
|
|
end
|
|
subfragments_liteethmacgap_state <= subfragments_liteethmacgap_next_state;
|
|
if (tx_gap_inserter_counter_liteethmacgap_next_value_ce) begin
|
|
tx_gap_inserter_counter <= tx_gap_inserter_counter_liteethmacgap_next_value;
|
|
end
|
|
subfragments_liteethmacpreambleinserter_state <= subfragments_liteethmacpreambleinserter_next_state;
|
|
if (preamble_inserter_count_liteethmacpreambleinserter_next_value_ce) begin
|
|
preamble_inserter_count <= preamble_inserter_count_liteethmacpreambleinserter_next_value;
|
|
end
|
|
if (liteethmaccrc32inserter_is_ongoing0) begin
|
|
liteethmaccrc32inserter_cnt <= 2'd3;
|
|
end else begin
|
|
if ((liteethmaccrc32inserter_is_ongoing1 & (~liteethmaccrc32inserter_cnt_done))) begin
|
|
liteethmaccrc32inserter_cnt <= (liteethmaccrc32inserter_cnt - liteethmaccrc32inserter_source_ready);
|
|
end
|
|
end
|
|
if (liteethmaccrc32inserter_ce) begin
|
|
liteethmaccrc32inserter_reg <= liteethmaccrc32inserter_next;
|
|
end
|
|
if (liteethmaccrc32inserter_reset) begin
|
|
liteethmaccrc32inserter_reg <= 32'd4294967295;
|
|
end
|
|
subfragments_liteethmaccrc32inserter_state <= subfragments_liteethmaccrc32inserter_next_state;
|
|
if (((~crc32_inserter_source_valid) | crc32_inserter_source_ready)) begin
|
|
crc32_inserter_source_valid <= crc32_inserter_sink_valid;
|
|
crc32_inserter_source_first <= crc32_inserter_sink_first;
|
|
crc32_inserter_source_last <= crc32_inserter_sink_last;
|
|
crc32_inserter_source_payload_data <= crc32_inserter_sink_payload_data;
|
|
crc32_inserter_source_payload_last_be <= crc32_inserter_sink_payload_last_be;
|
|
crc32_inserter_source_payload_error <= crc32_inserter_sink_payload_error;
|
|
end
|
|
subfragments_liteethmacpaddinginserter_state <= subfragments_liteethmacpaddinginserter_next_state;
|
|
if (padding_inserter_counter_liteethmacpaddinginserter_next_value_ce) begin
|
|
padding_inserter_counter <= padding_inserter_counter_liteethmacpaddinginserter_next_value;
|
|
end
|
|
subfragments_liteethmactxlastbe_state <= subfragments_liteethmactxlastbe_next_state;
|
|
if ((tx_converter_converter_source_valid & tx_converter_converter_source_ready)) begin
|
|
if (tx_converter_converter_last) begin
|
|
tx_converter_converter_mux <= 1'd0;
|
|
end else begin
|
|
tx_converter_converter_mux <= (tx_converter_converter_mux + 1'd1);
|
|
end
|
|
end
|
|
tx_cdc_cdc_graycounter1_q_binary <= tx_cdc_cdc_graycounter1_q_next_binary;
|
|
tx_cdc_cdc_graycounter1_q <= tx_cdc_cdc_graycounter1_q_next;
|
|
if (eth_tx_rst) begin
|
|
maccore_ethphy_liteethphygmiimiitx_gmii_tx_sink_ready <= 1'd0;
|
|
maccore_ethphy_liteethphygmiimiitx_converter_converter_mux <= 1'd0;
|
|
liteethmaccrc32inserter_reg <= 32'd4294967295;
|
|
liteethmaccrc32inserter_cnt <= 2'd3;
|
|
crc32_inserter_source_valid <= 1'd0;
|
|
crc32_inserter_source_payload_data <= 8'd0;
|
|
crc32_inserter_source_payload_last_be <= 1'd0;
|
|
crc32_inserter_source_payload_error <= 1'd0;
|
|
padding_inserter_counter <= 16'd0;
|
|
tx_converter_converter_mux <= 2'd0;
|
|
tx_cdc_cdc_graycounter1_q <= 6'd0;
|
|
tx_cdc_cdc_graycounter1_q_binary <= 6'd0;
|
|
subfragments_liteethmacgap_state <= 1'd0;
|
|
subfragments_liteethmacpreambleinserter_state <= 2'd0;
|
|
subfragments_liteethmaccrc32inserter_state <= 2'd0;
|
|
subfragments_liteethmacpaddinginserter_state <= 1'd0;
|
|
subfragments_liteethmactxlastbe_state <= 1'd0;
|
|
end
|
|
xilinxmultiregimpl4_regs0 <= tx_cdc_cdc_graycounter0_q;
|
|
xilinxmultiregimpl4_regs1 <= xilinxmultiregimpl4_regs0;
|
|
end
|
|
|
|
always @(posedge por_clk) begin
|
|
maccore_int_rst <= sys_reset;
|
|
end
|
|
|
|
always @(posedge sys_clk) begin
|
|
if ((maccore_maccore_bus_errors != 32'd4294967295)) begin
|
|
if (maccore_maccore_bus_error) begin
|
|
maccore_maccore_bus_errors <= (maccore_maccore_bus_errors + 1'd1);
|
|
end
|
|
end
|
|
if (maccore_ethphy_update_mode) begin
|
|
maccore_ethphy_mode0 <= maccore_ethphy_mode1;
|
|
end
|
|
if (maccore_ethphy_sys_counter_reset) begin
|
|
maccore_ethphy_sys_counter <= 1'd0;
|
|
end else begin
|
|
if (maccore_ethphy_sys_counter_ce) begin
|
|
maccore_ethphy_sys_counter <= (maccore_ethphy_sys_counter + 1'd1);
|
|
end
|
|
end
|
|
maccore_ethphy_toggle_o_r <= maccore_ethphy_toggle_o;
|
|
subfragments_state <= subfragments_next_state;
|
|
if (maccore_ethphy_counter_ce) begin
|
|
maccore_ethphy_counter <= (maccore_ethphy_counter + 1'd1);
|
|
end
|
|
if (ps_preamble_error_o) begin
|
|
preamble_errors_status <= (preamble_errors_status + 1'd1);
|
|
end
|
|
if (ps_crc_error_o) begin
|
|
crc_errors_status <= (crc_errors_status + 1'd1);
|
|
end
|
|
ps_preamble_error_toggle_o_r <= ps_preamble_error_toggle_o;
|
|
ps_crc_error_toggle_o_r <= ps_crc_error_toggle_o;
|
|
tx_cdc_cdc_graycounter0_q_binary <= tx_cdc_cdc_graycounter0_q_next_binary;
|
|
tx_cdc_cdc_graycounter0_q <= tx_cdc_cdc_graycounter0_q_next;
|
|
rx_cdc_cdc_graycounter1_q_binary <= rx_cdc_cdc_graycounter1_q_next_binary;
|
|
rx_cdc_cdc_graycounter1_q <= rx_cdc_cdc_graycounter1_q_next;
|
|
if (writer_slot_ce) begin
|
|
writer_slot <= (writer_slot + 1'd1);
|
|
end
|
|
if (((writer_stat_fifo_syncfifo_we & writer_stat_fifo_syncfifo_writable) & (~writer_stat_fifo_replace))) begin
|
|
writer_stat_fifo_produce <= (writer_stat_fifo_produce + 1'd1);
|
|
end
|
|
if (writer_stat_fifo_do_read) begin
|
|
writer_stat_fifo_consume <= (writer_stat_fifo_consume + 1'd1);
|
|
end
|
|
if (((writer_stat_fifo_syncfifo_we & writer_stat_fifo_syncfifo_writable) & (~writer_stat_fifo_replace))) begin
|
|
if ((~writer_stat_fifo_do_read)) begin
|
|
writer_stat_fifo_level <= (writer_stat_fifo_level + 1'd1);
|
|
end
|
|
end else begin
|
|
if (writer_stat_fifo_do_read) begin
|
|
writer_stat_fifo_level <= (writer_stat_fifo_level - 1'd1);
|
|
end
|
|
end
|
|
subfragments_liteethmacsramwriter_state <= subfragments_liteethmacsramwriter_next_state;
|
|
if (writer_counter_t_next_value_ce) begin
|
|
writer_counter <= writer_counter_t_next_value;
|
|
end
|
|
if (writer_errors_status_f_next_value_ce) begin
|
|
writer_errors_status <= writer_errors_status_f_next_value;
|
|
end
|
|
if (reader_eventsourcepulse_clear) begin
|
|
reader_eventsourcepulse_pending <= 1'd0;
|
|
end
|
|
if (reader_eventsourcepulse_trigger) begin
|
|
reader_eventsourcepulse_pending <= 1'd1;
|
|
end
|
|
if (((reader_cmd_fifo_syncfifo_we & reader_cmd_fifo_syncfifo_writable) & (~reader_cmd_fifo_replace))) begin
|
|
reader_cmd_fifo_produce <= (reader_cmd_fifo_produce + 1'd1);
|
|
end
|
|
if (reader_cmd_fifo_do_read) begin
|
|
reader_cmd_fifo_consume <= (reader_cmd_fifo_consume + 1'd1);
|
|
end
|
|
if (((reader_cmd_fifo_syncfifo_we & reader_cmd_fifo_syncfifo_writable) & (~reader_cmd_fifo_replace))) begin
|
|
if ((~reader_cmd_fifo_do_read)) begin
|
|
reader_cmd_fifo_level <= (reader_cmd_fifo_level + 1'd1);
|
|
end
|
|
end else begin
|
|
if (reader_cmd_fifo_do_read) begin
|
|
reader_cmd_fifo_level <= (reader_cmd_fifo_level - 1'd1);
|
|
end
|
|
end
|
|
subfragments_liteethmacsramreader_state <= subfragments_liteethmacsramreader_next_state;
|
|
if (reader_counter_next_value_ce) begin
|
|
reader_counter <= reader_counter_next_value;
|
|
end
|
|
sram0_bus_ack0 <= 1'd0;
|
|
if (((sram0_bus_cyc0 & sram0_bus_stb0) & (~sram0_bus_ack0))) begin
|
|
sram0_bus_ack0 <= 1'd1;
|
|
end
|
|
sram1_bus_ack0 <= 1'd0;
|
|
if (((sram1_bus_cyc0 & sram1_bus_stb0) & (~sram1_bus_ack0))) begin
|
|
sram1_bus_ack0 <= 1'd1;
|
|
end
|
|
sram0_bus_ack1 <= 1'd0;
|
|
if (((sram0_bus_cyc1 & sram0_bus_stb1) & (~sram0_bus_ack1))) begin
|
|
sram0_bus_ack1 <= 1'd1;
|
|
end
|
|
sram1_bus_ack1 <= 1'd0;
|
|
if (((sram1_bus_cyc1 & sram1_bus_stb1) & (~sram1_bus_ack1))) begin
|
|
sram1_bus_ack1 <= 1'd1;
|
|
end
|
|
slave_sel_r <= slave_sel;
|
|
maccore_state <= maccore_next_state;
|
|
maccore_slave_sel_r <= maccore_slave_sel;
|
|
if (maccore_wait) begin
|
|
if ((~maccore_done)) begin
|
|
maccore_count <= (maccore_count - 1'd1);
|
|
end
|
|
end else begin
|
|
maccore_count <= 20'd1000000;
|
|
end
|
|
maccore_interface0_bank_bus_dat_r <= 1'd0;
|
|
if (maccore_csrbank0_sel) begin
|
|
case (maccore_interface0_bank_bus_adr[8:0])
|
|
1'd0: begin
|
|
maccore_interface0_bank_bus_dat_r <= maccore_csrbank0_reset0_w;
|
|
end
|
|
1'd1: begin
|
|
maccore_interface0_bank_bus_dat_r <= maccore_csrbank0_scratch0_w;
|
|
end
|
|
2'd2: begin
|
|
maccore_interface0_bank_bus_dat_r <= maccore_csrbank0_bus_errors_w;
|
|
end
|
|
endcase
|
|
end
|
|
if (maccore_csrbank0_reset0_re) begin
|
|
maccore_maccore_reset_storage[1:0] <= maccore_csrbank0_reset0_r;
|
|
end
|
|
maccore_maccore_reset_re <= maccore_csrbank0_reset0_re;
|
|
if (maccore_csrbank0_scratch0_re) begin
|
|
maccore_maccore_scratch_storage[31:0] <= maccore_csrbank0_scratch0_r;
|
|
end
|
|
maccore_maccore_scratch_re <= maccore_csrbank0_scratch0_re;
|
|
maccore_maccore_bus_errors_re <= maccore_csrbank0_bus_errors_re;
|
|
maccore_interface1_bank_bus_dat_r <= 1'd0;
|
|
if (maccore_csrbank1_sel) begin
|
|
case (maccore_interface1_bank_bus_adr[8:0])
|
|
1'd0: begin
|
|
maccore_interface1_bank_bus_dat_r <= maccore_csrbank1_sram_writer_slot_w;
|
|
end
|
|
1'd1: begin
|
|
maccore_interface1_bank_bus_dat_r <= maccore_csrbank1_sram_writer_length_w;
|
|
end
|
|
2'd2: begin
|
|
maccore_interface1_bank_bus_dat_r <= maccore_csrbank1_sram_writer_errors_w;
|
|
end
|
|
2'd3: begin
|
|
maccore_interface1_bank_bus_dat_r <= maccore_csrbank1_sram_writer_ev_status_w;
|
|
end
|
|
3'd4: begin
|
|
maccore_interface1_bank_bus_dat_r <= maccore_csrbank1_sram_writer_ev_pending_w;
|
|
end
|
|
3'd5: begin
|
|
maccore_interface1_bank_bus_dat_r <= maccore_csrbank1_sram_writer_ev_enable0_w;
|
|
end
|
|
3'd6: begin
|
|
maccore_interface1_bank_bus_dat_r <= reader_start_start_w;
|
|
end
|
|
3'd7: begin
|
|
maccore_interface1_bank_bus_dat_r <= maccore_csrbank1_sram_reader_ready_w;
|
|
end
|
|
4'd8: begin
|
|
maccore_interface1_bank_bus_dat_r <= maccore_csrbank1_sram_reader_level_w;
|
|
end
|
|
4'd9: begin
|
|
maccore_interface1_bank_bus_dat_r <= maccore_csrbank1_sram_reader_slot0_w;
|
|
end
|
|
4'd10: begin
|
|
maccore_interface1_bank_bus_dat_r <= maccore_csrbank1_sram_reader_length0_w;
|
|
end
|
|
4'd11: begin
|
|
maccore_interface1_bank_bus_dat_r <= maccore_csrbank1_sram_reader_ev_status_w;
|
|
end
|
|
4'd12: begin
|
|
maccore_interface1_bank_bus_dat_r <= maccore_csrbank1_sram_reader_ev_pending_w;
|
|
end
|
|
4'd13: begin
|
|
maccore_interface1_bank_bus_dat_r <= maccore_csrbank1_sram_reader_ev_enable0_w;
|
|
end
|
|
4'd14: begin
|
|
maccore_interface1_bank_bus_dat_r <= maccore_csrbank1_preamble_crc_w;
|
|
end
|
|
4'd15: begin
|
|
maccore_interface1_bank_bus_dat_r <= maccore_csrbank1_preamble_errors_w;
|
|
end
|
|
5'd16: begin
|
|
maccore_interface1_bank_bus_dat_r <= maccore_csrbank1_crc_errors_w;
|
|
end
|
|
endcase
|
|
end
|
|
writer_slot_re <= maccore_csrbank1_sram_writer_slot_re;
|
|
writer_length_re <= maccore_csrbank1_sram_writer_length_re;
|
|
writer_errors_re <= maccore_csrbank1_sram_writer_errors_re;
|
|
writer_status_re <= maccore_csrbank1_sram_writer_ev_status_re;
|
|
if (maccore_csrbank1_sram_writer_ev_pending_re) begin
|
|
writer_pending_r <= maccore_csrbank1_sram_writer_ev_pending_r;
|
|
end
|
|
writer_pending_re <= maccore_csrbank1_sram_writer_ev_pending_re;
|
|
if (maccore_csrbank1_sram_writer_ev_enable0_re) begin
|
|
writer_enable_storage <= maccore_csrbank1_sram_writer_ev_enable0_r;
|
|
end
|
|
writer_enable_re <= maccore_csrbank1_sram_writer_ev_enable0_re;
|
|
reader_ready_re <= maccore_csrbank1_sram_reader_ready_re;
|
|
reader_level_re <= maccore_csrbank1_sram_reader_level_re;
|
|
if (maccore_csrbank1_sram_reader_slot0_re) begin
|
|
reader_slot_storage <= maccore_csrbank1_sram_reader_slot0_r;
|
|
end
|
|
reader_slot_re <= maccore_csrbank1_sram_reader_slot0_re;
|
|
if (maccore_csrbank1_sram_reader_length0_re) begin
|
|
reader_length_storage[10:0] <= maccore_csrbank1_sram_reader_length0_r;
|
|
end
|
|
reader_length_re <= maccore_csrbank1_sram_reader_length0_re;
|
|
reader_status_re <= maccore_csrbank1_sram_reader_ev_status_re;
|
|
if (maccore_csrbank1_sram_reader_ev_pending_re) begin
|
|
reader_pending_r <= maccore_csrbank1_sram_reader_ev_pending_r;
|
|
end
|
|
reader_pending_re <= maccore_csrbank1_sram_reader_ev_pending_re;
|
|
if (maccore_csrbank1_sram_reader_ev_enable0_re) begin
|
|
reader_enable_storage <= maccore_csrbank1_sram_reader_ev_enable0_r;
|
|
end
|
|
reader_enable_re <= maccore_csrbank1_sram_reader_ev_enable0_re;
|
|
preamble_crc_re <= maccore_csrbank1_preamble_crc_re;
|
|
preamble_errors_re <= maccore_csrbank1_preamble_errors_re;
|
|
crc_errors_re <= maccore_csrbank1_crc_errors_re;
|
|
maccore_interface2_bank_bus_dat_r <= 1'd0;
|
|
if (maccore_csrbank2_sel) begin
|
|
case (maccore_interface2_bank_bus_adr[8:0])
|
|
1'd0: begin
|
|
maccore_interface2_bank_bus_dat_r <= maccore_csrbank2_mode_detection_mode_w;
|
|
end
|
|
1'd1: begin
|
|
maccore_interface2_bank_bus_dat_r <= maccore_csrbank2_crg_reset0_w;
|
|
end
|
|
2'd2: begin
|
|
maccore_interface2_bank_bus_dat_r <= maccore_csrbank2_mdio_w0_w;
|
|
end
|
|
2'd3: begin
|
|
maccore_interface2_bank_bus_dat_r <= maccore_csrbank2_mdio_r_w;
|
|
end
|
|
endcase
|
|
end
|
|
maccore_ethphy_mode_re <= maccore_csrbank2_mode_detection_mode_re;
|
|
if (maccore_csrbank2_crg_reset0_re) begin
|
|
maccore_ethphy_reset_storage <= maccore_csrbank2_crg_reset0_r;
|
|
end
|
|
maccore_ethphy_reset_re <= maccore_csrbank2_crg_reset0_re;
|
|
if (maccore_csrbank2_mdio_w0_re) begin
|
|
maccore_ethphy__w_storage[2:0] <= maccore_csrbank2_mdio_w0_r;
|
|
end
|
|
maccore_ethphy__w_re <= maccore_csrbank2_mdio_w0_re;
|
|
maccore_ethphy__r_re <= maccore_csrbank2_mdio_r_re;
|
|
if (sys_rst) begin
|
|
maccore_maccore_reset_storage <= 2'd0;
|
|
maccore_maccore_reset_re <= 1'd0;
|
|
maccore_maccore_scratch_storage <= 32'd305419896;
|
|
maccore_maccore_scratch_re <= 1'd0;
|
|
maccore_maccore_bus_errors_re <= 1'd0;
|
|
maccore_maccore_bus_errors <= 32'd0;
|
|
maccore_ethphy_mode0 <= 1'd0;
|
|
maccore_ethphy_mode_re <= 1'd0;
|
|
maccore_ethphy_reset_storage <= 1'd0;
|
|
maccore_ethphy_reset_re <= 1'd0;
|
|
maccore_ethphy_counter <= 9'd0;
|
|
maccore_ethphy__w_storage <= 3'd0;
|
|
maccore_ethphy__w_re <= 1'd0;
|
|
maccore_ethphy__r_re <= 1'd0;
|
|
preamble_crc_re <= 1'd0;
|
|
preamble_errors_status <= 32'd0;
|
|
preamble_errors_re <= 1'd0;
|
|
crc_errors_status <= 32'd0;
|
|
crc_errors_re <= 1'd0;
|
|
tx_cdc_cdc_graycounter0_q <= 6'd0;
|
|
tx_cdc_cdc_graycounter0_q_binary <= 6'd0;
|
|
rx_cdc_cdc_graycounter1_q <= 6'd0;
|
|
rx_cdc_cdc_graycounter1_q_binary <= 6'd0;
|
|
writer_slot_re <= 1'd0;
|
|
writer_length_re <= 1'd0;
|
|
writer_errors_status <= 32'd0;
|
|
writer_errors_re <= 1'd0;
|
|
writer_status_re <= 1'd0;
|
|
writer_pending_re <= 1'd0;
|
|
writer_pending_r <= 1'd0;
|
|
writer_enable_storage <= 1'd0;
|
|
writer_enable_re <= 1'd0;
|
|
writer_counter <= 32'd0;
|
|
writer_slot <= 1'd0;
|
|
writer_stat_fifo_level <= 2'd0;
|
|
writer_stat_fifo_produce <= 1'd0;
|
|
writer_stat_fifo_consume <= 1'd0;
|
|
reader_ready_re <= 1'd0;
|
|
reader_level_re <= 1'd0;
|
|
reader_slot_re <= 1'd0;
|
|
reader_length_re <= 1'd0;
|
|
reader_eventsourcepulse_pending <= 1'd0;
|
|
reader_status_re <= 1'd0;
|
|
reader_pending_re <= 1'd0;
|
|
reader_pending_r <= 1'd0;
|
|
reader_enable_storage <= 1'd0;
|
|
reader_enable_re <= 1'd0;
|
|
reader_cmd_fifo_level <= 2'd0;
|
|
reader_cmd_fifo_produce <= 1'd0;
|
|
reader_cmd_fifo_consume <= 1'd0;
|
|
reader_counter <= 11'd0;
|
|
sram0_bus_ack0 <= 1'd0;
|
|
sram1_bus_ack0 <= 1'd0;
|
|
sram0_bus_ack1 <= 1'd0;
|
|
sram1_bus_ack1 <= 1'd0;
|
|
slave_sel_r <= 4'd0;
|
|
subfragments_state <= 2'd0;
|
|
subfragments_liteethmacsramwriter_state <= 3'd0;
|
|
subfragments_liteethmacsramreader_state <= 2'd0;
|
|
maccore_slave_sel_r <= 2'd0;
|
|
maccore_count <= 20'd1000000;
|
|
maccore_state <= 1'd0;
|
|
end
|
|
xilinxmultiregimpl0_regs0 <= maccore_ethphy_toggle_i;
|
|
xilinxmultiregimpl0_regs1 <= xilinxmultiregimpl0_regs0;
|
|
xilinxmultiregimpl1_regs0 <= maccore_ethphy_data_r;
|
|
xilinxmultiregimpl1_regs1 <= xilinxmultiregimpl1_regs0;
|
|
xilinxmultiregimpl2_regs0 <= ps_preamble_error_toggle_i;
|
|
xilinxmultiregimpl2_regs1 <= xilinxmultiregimpl2_regs0;
|
|
xilinxmultiregimpl3_regs0 <= ps_crc_error_toggle_i;
|
|
xilinxmultiregimpl3_regs1 <= xilinxmultiregimpl3_regs0;
|
|
xilinxmultiregimpl5_regs0 <= tx_cdc_cdc_graycounter1_q;
|
|
xilinxmultiregimpl5_regs1 <= xilinxmultiregimpl5_regs0;
|
|
xilinxmultiregimpl6_regs0 <= rx_cdc_cdc_graycounter0_q;
|
|
xilinxmultiregimpl6_regs1 <= xilinxmultiregimpl6_regs0;
|
|
end
|
|
|
|
BUFG BUFG(
|
|
.I(gmii_eth_clocks_rx),
|
|
.O(eth_rx_clk)
|
|
);
|
|
|
|
BUFG BUFG_1(
|
|
.I(maccore_ethphy_eth_tx_clk),
|
|
.O(eth_tx_clk)
|
|
);
|
|
|
|
assign gmii_eth_mdio = maccore_ethphy_data_oe ? maccore_ethphy_data_w : 1'bz;
|
|
assign maccore_ethphy_data_r = gmii_eth_mdio;
|
|
|
|
reg [11:0] storage[0:4];
|
|
reg [11:0] memdat;
|
|
always @(posedge eth_rx_clk) begin
|
|
if (liteethmaccrc32checker_syncfifo_wrport_we)
|
|
storage[liteethmaccrc32checker_syncfifo_wrport_adr] <= liteethmaccrc32checker_syncfifo_wrport_dat_w;
|
|
memdat <= storage[liteethmaccrc32checker_syncfifo_wrport_adr];
|
|
end
|
|
|
|
always @(posedge eth_rx_clk) begin
|
|
end
|
|
|
|
assign liteethmaccrc32checker_syncfifo_wrport_dat_r = memdat;
|
|
assign liteethmaccrc32checker_syncfifo_rdport_dat_r = storage[liteethmaccrc32checker_syncfifo_rdport_adr];
|
|
|
|
reg [41:0] storage_1[0:31];
|
|
reg [4:0] memadr;
|
|
reg [4:0] memadr_1;
|
|
always @(posedge sys_clk) begin
|
|
if (tx_cdc_cdc_wrport_we)
|
|
storage_1[tx_cdc_cdc_wrport_adr] <= tx_cdc_cdc_wrport_dat_w;
|
|
memadr <= tx_cdc_cdc_wrport_adr;
|
|
end
|
|
|
|
always @(posedge eth_tx_clk) begin
|
|
memadr_1 <= tx_cdc_cdc_rdport_adr;
|
|
end
|
|
|
|
assign tx_cdc_cdc_wrport_dat_r = storage_1[memadr];
|
|
assign tx_cdc_cdc_rdport_dat_r = storage_1[memadr_1];
|
|
|
|
reg [41:0] storage_2[0:31];
|
|
reg [4:0] memadr_2;
|
|
reg [4:0] memadr_3;
|
|
always @(posedge eth_rx_clk) begin
|
|
if (rx_cdc_cdc_wrport_we)
|
|
storage_2[rx_cdc_cdc_wrport_adr] <= rx_cdc_cdc_wrport_dat_w;
|
|
memadr_2 <= rx_cdc_cdc_wrport_adr;
|
|
end
|
|
|
|
always @(posedge sys_clk) begin
|
|
memadr_3 <= rx_cdc_cdc_rdport_adr;
|
|
end
|
|
|
|
assign rx_cdc_cdc_wrport_dat_r = storage_2[memadr_2];
|
|
assign rx_cdc_cdc_rdport_dat_r = storage_2[memadr_3];
|
|
|
|
reg [34:0] storage_3[0:1];
|
|
reg [34:0] memdat_1;
|
|
always @(posedge sys_clk) begin
|
|
if (writer_stat_fifo_wrport_we)
|
|
storage_3[writer_stat_fifo_wrport_adr] <= writer_stat_fifo_wrport_dat_w;
|
|
memdat_1 <= storage_3[writer_stat_fifo_wrport_adr];
|
|
end
|
|
|
|
always @(posedge sys_clk) begin
|
|
end
|
|
|
|
assign writer_stat_fifo_wrport_dat_r = memdat_1;
|
|
assign writer_stat_fifo_rdport_dat_r = storage_3[writer_stat_fifo_rdport_adr];
|
|
|
|
reg [31:0] mem[0:381];
|
|
reg [8:0] memadr_4;
|
|
reg [31:0] memdat_2;
|
|
always @(posedge sys_clk) begin
|
|
if (writer_memory0_we)
|
|
mem[writer_memory0_adr] <= writer_memory0_dat_w;
|
|
memadr_4 <= writer_memory0_adr;
|
|
end
|
|
|
|
always @(posedge sys_clk) begin
|
|
memdat_2 <= mem[sram0_adr0];
|
|
end
|
|
|
|
assign writer_memory0_dat_r = mem[memadr_4];
|
|
assign sram0_dat_r0 = memdat_2;
|
|
|
|
reg [31:0] mem_1[0:381];
|
|
reg [8:0] memadr_5;
|
|
reg [31:0] memdat_3;
|
|
always @(posedge sys_clk) begin
|
|
if (writer_memory1_we)
|
|
mem_1[writer_memory1_adr] <= writer_memory1_dat_w;
|
|
memadr_5 <= writer_memory1_adr;
|
|
end
|
|
|
|
always @(posedge sys_clk) begin
|
|
memdat_3 <= mem_1[sram1_adr0];
|
|
end
|
|
|
|
assign writer_memory1_dat_r = mem_1[memadr_5];
|
|
assign sram1_dat_r0 = memdat_3;
|
|
|
|
reg [13:0] storage_4[0:1];
|
|
reg [13:0] memdat_4;
|
|
always @(posedge sys_clk) begin
|
|
if (reader_cmd_fifo_wrport_we)
|
|
storage_4[reader_cmd_fifo_wrport_adr] <= reader_cmd_fifo_wrport_dat_w;
|
|
memdat_4 <= storage_4[reader_cmd_fifo_wrport_adr];
|
|
end
|
|
|
|
always @(posedge sys_clk) begin
|
|
end
|
|
|
|
assign reader_cmd_fifo_wrport_dat_r = memdat_4;
|
|
assign reader_cmd_fifo_rdport_dat_r = storage_4[reader_cmd_fifo_rdport_adr];
|
|
|
|
reg [31:0] mem_2[0:381];
|
|
reg [8:0] memadr_6;
|
|
reg [8:0] memadr_7;
|
|
always @(posedge sys_clk) begin
|
|
memadr_6 <= reader_memory0_adr;
|
|
end
|
|
|
|
always @(posedge sys_clk) begin
|
|
if (sram0_we[0])
|
|
mem_2[sram0_adr1][7:0] <= sram0_dat_w[7:0];
|
|
if (sram0_we[1])
|
|
mem_2[sram0_adr1][15:8] <= sram0_dat_w[15:8];
|
|
if (sram0_we[2])
|
|
mem_2[sram0_adr1][23:16] <= sram0_dat_w[23:16];
|
|
if (sram0_we[3])
|
|
mem_2[sram0_adr1][31:24] <= sram0_dat_w[31:24];
|
|
memadr_7 <= sram0_adr1;
|
|
end
|
|
|
|
assign reader_memory0_dat_r = mem_2[memadr_6];
|
|
assign sram0_dat_r1 = mem_2[memadr_7];
|
|
|
|
reg [31:0] mem_3[0:381];
|
|
reg [8:0] memadr_8;
|
|
reg [8:0] memadr_9;
|
|
always @(posedge sys_clk) begin
|
|
memadr_8 <= reader_memory1_adr;
|
|
end
|
|
|
|
always @(posedge sys_clk) begin
|
|
if (sram1_we[0])
|
|
mem_3[sram1_adr1][7:0] <= sram1_dat_w[7:0];
|
|
if (sram1_we[1])
|
|
mem_3[sram1_adr1][15:8] <= sram1_dat_w[15:8];
|
|
if (sram1_we[2])
|
|
mem_3[sram1_adr1][23:16] <= sram1_dat_w[23:16];
|
|
if (sram1_we[3])
|
|
mem_3[sram1_adr1][31:24] <= sram1_dat_w[31:24];
|
|
memadr_9 <= sram1_adr1;
|
|
end
|
|
|
|
assign reader_memory1_dat_r = mem_3[memadr_8];
|
|
assign sram1_dat_r1 = mem_3[memadr_9];
|
|
|
|
ODDR #(
|
|
.DDR_CLK_EDGE("SAME_EDGE")
|
|
) ODDR (
|
|
.C(eth_tx_clk),
|
|
.CE(1'd1),
|
|
.D1(1'd1),
|
|
.D2((maccore_ethphy_mode0 == 1'd1)),
|
|
.R(1'd0),
|
|
.S(1'd0),
|
|
.Q(gmii_eth_clocks_gtx)
|
|
);
|
|
|
|
(* ars_ff1 = "true", async_reg = "true" *) FDPE #(
|
|
.INIT(1'd1)
|
|
) FDPE (
|
|
.C(eth_tx_clk),
|
|
.CE(1'd1),
|
|
.D(1'd0),
|
|
.PRE(maccore_ethphy_reset0),
|
|
.Q(rst_meta0)
|
|
);
|
|
|
|
(* ars_ff2 = "true", async_reg = "true" *) FDPE #(
|
|
.INIT(1'd1)
|
|
) FDPE_1 (
|
|
.C(eth_tx_clk),
|
|
.CE(1'd1),
|
|
.D(rst_meta0),
|
|
.PRE(maccore_ethphy_reset0),
|
|
.Q(eth_tx_rst)
|
|
);
|
|
|
|
(* ars_ff1 = "true", async_reg = "true" *) FDPE #(
|
|
.INIT(1'd1)
|
|
) FDPE_2 (
|
|
.C(eth_rx_clk),
|
|
.CE(1'd1),
|
|
.D(1'd0),
|
|
.PRE(maccore_ethphy_reset0),
|
|
.Q(rst_meta1)
|
|
);
|
|
|
|
(* ars_ff2 = "true", async_reg = "true" *) FDPE #(
|
|
.INIT(1'd1)
|
|
) FDPE_3 (
|
|
.C(eth_rx_clk),
|
|
.CE(1'd1),
|
|
.D(rst_meta1),
|
|
.PRE(maccore_ethphy_reset0),
|
|
.Q(eth_rx_rst)
|
|
);
|
|
|
|
endmodule
|