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131 lines
4.0 KiB
VHDL
131 lines
4.0 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.helpers.all;
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entity bit_counter is
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port (
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clk : in std_logic;
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rs : in std_ulogic_vector(63 downto 0);
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count_right : in std_ulogic;
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do_popcnt : in std_ulogic;
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is_32bit : in std_ulogic;
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datalen : in std_ulogic_vector(3 downto 0);
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result : out std_ulogic_vector(63 downto 0)
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);
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end entity bit_counter;
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architecture behaviour of bit_counter is
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-- signals for count-leading/trailing-zeroes
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signal inp : std_ulogic_vector(63 downto 0);
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signal sum : std_ulogic_vector(64 downto 0);
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signal msb_r : std_ulogic;
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signal onehot : std_ulogic_vector(63 downto 0);
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signal onehot_r : std_ulogic_vector(63 downto 0);
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signal bitnum : std_ulogic_vector(5 downto 0);
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signal cntz : std_ulogic_vector(63 downto 0);
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-- signals for popcnt
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signal dlen_r : std_ulogic_vector(3 downto 0);
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signal pcnt_r : std_ulogic;
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subtype twobit is unsigned(1 downto 0);
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type twobit32 is array(0 to 31) of twobit;
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signal pc2 : twobit32;
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subtype threebit is unsigned(2 downto 0);
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type threebit16 is array(0 to 15) of threebit;
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signal pc4 : threebit16;
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subtype fourbit is unsigned(3 downto 0);
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type fourbit8 is array(0 to 7) of fourbit;
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signal pc8 : fourbit8;
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signal pc8_r : fourbit8;
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subtype sixbit is unsigned(5 downto 0);
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type sixbit2 is array(0 to 1) of sixbit;
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signal pc32 : sixbit2;
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signal popcnt : std_ulogic_vector(63 downto 0);
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begin
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countzero_r: process(clk)
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begin
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if rising_edge(clk) then
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msb_r <= sum(64);
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onehot_r <= onehot;
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end if;
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end process;
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countzero: process(all)
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begin
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if is_32bit = '0' then
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if count_right = '0' then
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inp <= bit_reverse(rs);
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else
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inp <= rs;
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end if;
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else
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inp(63 downto 32) <= x"FFFFFFFF";
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if count_right = '0' then
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inp(31 downto 0) <= bit_reverse(rs(31 downto 0));
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else
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inp(31 downto 0) <= rs(31 downto 0);
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end if;
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end if;
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sum <= std_ulogic_vector(unsigned('0' & not inp) + 1);
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onehot <= sum(63 downto 0) and inp;
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-- The following occurs after a clock edge
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bitnum <= bit_number(onehot_r);
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cntz <= 57x"0" & msb_r & bitnum;
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end process;
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popcnt_r: process(clk)
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begin
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if rising_edge(clk) then
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for i in 0 to 7 loop
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pc8_r(i) <= pc8(i);
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end loop;
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dlen_r <= datalen;
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pcnt_r <= do_popcnt;
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end if;
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end process;
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popcnt_a: process(all)
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begin
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for i in 0 to 31 loop
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pc2(i) <= unsigned("0" & rs(i * 2 downto i * 2)) + unsigned("0" & rs(i * 2 + 1 downto i * 2 + 1));
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end loop;
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for i in 0 to 15 loop
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pc4(i) <= ('0' & pc2(i * 2)) + ('0' & pc2(i * 2 + 1));
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end loop;
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for i in 0 to 7 loop
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pc8(i) <= ('0' & pc4(i * 2)) + ('0' & pc4(i * 2 + 1));
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end loop;
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-- after a clock edge
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for i in 0 to 1 loop
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pc32(i) <= ("00" & pc8_r(i * 4)) + ("00" & pc8_r(i * 4 + 1)) +
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("00" & pc8_r(i * 4 + 2)) + ("00" & pc8_r(i * 4 + 3));
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end loop;
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popcnt <= (others => '0');
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if dlen_r(3 downto 2) = "00" then
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-- popcntb
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for i in 0 to 7 loop
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popcnt(i * 8 + 3 downto i * 8) <= std_ulogic_vector(pc8_r(i));
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end loop;
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elsif dlen_r(3) = '0' then
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-- popcntw
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for i in 0 to 1 loop
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popcnt(i * 32 + 5 downto i * 32) <= std_ulogic_vector(pc32(i));
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end loop;
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else
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popcnt(6 downto 0) <= std_ulogic_vector(('0' & pc32(0)) + ('0' & pc32(1)));
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end if;
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end process;
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result <= cntz when pcnt_r = '0' else popcnt;
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end behaviour;
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