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Michael Neuling
4d5abfb430
Some VHDL compilers like verific [1] don't like these, so let's remove them. Lots of random code changes, but passes make check. Also add basic script to run verific and generate verilog. 1. https://www.verific.com/ Signed-off-by: Michael Neuling <mikey@neuling.org> |
5 years ago | |
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.. | ||
dependencies.py | ||
hash.py | ||
run_test.sh | ||
test_micropython.py | ||
test_micropython_long.py | ||
verific.sh | 5 years ago |