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Anton Blanchard 6cbf456388 SOC memory wishbone should clear ACK regardless of STB 
The memory wishbone doesn't clear ACK and move the state machine on
until STB is de-asserted. This seems like it isn't compliant with
the spec and results in a maximum throughput of 1 transfer every
3 cycles.

Fixing this improves the situation to one transfer every 2 cycles.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
..
LICENSE Initial import of microwatt
arty_a7-35.xdc Merge pull request from antonblanchard/reset-rework2
clk_gen_bypass.vhd Fix clk_gen_bypass
clk_gen_mcmm.vhd Remove names from end record statements
clk_gen_plle2.vhd Remove names from end record statements
cmod_a7-35.xdc Cmod A7-35 support
firmware.hex Add a few more FPGA related files
hello_world.hex Rebuild hello world assuming a 50MHz clock
mw_soc_memory.vhdl SOC memory wishbone should clear ACK regardless of STB
nexys-video.xdc Rename a few reset signals
nexys_a7.xdc Merge pull request from antonblanchard/reset-rework2
nodivide.patch Add a few more FPGA related files
pp_fifo.vhd Initial import of microwatt
pp_soc_uart.vhd Initial import of microwatt
pp_utilities.vhd Initial import of microwatt
soc_reset.vhdl Rework SOC reset
soc_reset_tb.vhdl Rework SOC reset
toplevel.vhdl Share soc.vhdl between FPGA and sim