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393 lines
12 KiB
VHDL
393 lines
12 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.decode_types.all;
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use work.common.all;
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use work.helpers.all;
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use work.crhelpers.all;
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use work.ppc_fx_insns.all;
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use work.sim_console.all;
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entity execute1 is
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generic (
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SIM : boolean := false
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);
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port (
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clk : in std_logic;
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-- asynchronous
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flush_out : out std_ulogic;
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e_in : in Decode2ToExecute1Type;
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-- asynchronous
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f_out : out Execute1ToFetch1Type;
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e_out : out Execute1ToExecute2Type;
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terminate_out : out std_ulogic
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);
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end entity execute1;
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architecture behaviour of execute1 is
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type reg_type is record
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--f : Execute1ToFetch1Type;
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e : Execute1ToExecute2Type;
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end record;
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signal r, rin : reg_type;
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signal ctrl: ctrl_t := (carry => '0', others => (others => '0'));
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signal ctrl_tmp: ctrl_t := (carry => '0', others => (others => '0'));
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begin
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execute1_0: process(clk)
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begin
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if rising_edge(clk) then
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r <= rin;
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ctrl <= ctrl_tmp;
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end if;
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end process;
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execute1_1: process(all)
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variable v : reg_type;
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variable result : std_ulogic_vector(63 downto 0);
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variable result_with_carry : std_ulogic_vector(64 downto 0);
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variable result_en : integer;
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variable crnum : integer;
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variable lo, hi : integer;
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begin
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result := (others => '0');
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result_with_carry := (others => '0');
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result_en := 0;
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v := r;
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v.e := Execute1ToExecute2Init;
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--v.f := Execute1ToFetch1TypeInit;
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ctrl_tmp <= ctrl;
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-- FIXME: run at 512MHz not core freq
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ctrl_tmp.tb <= std_ulogic_vector(unsigned(ctrl.tb) + 1);
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terminate_out <= '0';
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flush_out <= '0';
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f_out <= Execute1ToFetch1TypeInit;
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if e_in.valid = '1' then
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v.e.valid := '1';
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v.e.write_reg := e_in.write_reg;
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case_0: case e_in.insn_type is
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when OP_ILLEGAL =>
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terminate_out <= '1';
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report "illegal";
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when OP_NOP =>
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-- Do nothing
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when OP_ADD =>
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result := ppc_add(e_in.read_data1, e_in.read_data2);
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result_en := 1;
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when OP_ADDC =>
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result_with_carry := ppc_adde(e_in.read_data1, e_in.read_data2, ctrl.carry and e_in.input_carry);
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result := result_with_carry(63 downto 0);
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ctrl_tmp.carry <= result_with_carry(64) and e_in.output_carry;
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result_en := 1;
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when OP_AND =>
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result := ppc_and(e_in.read_data1, e_in.read_data2);
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result_en := 1;
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when OP_ANDC =>
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result := ppc_andc(e_in.read_data1, e_in.read_data2);
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result_en := 1;
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when OP_B =>
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flush_out <= '1';
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f_out.redirect <= '1';
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f_out.redirect_nia <= std_ulogic_vector(signed(e_in.nia) + signed(e_in.read_data2));
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when OP_BC =>
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if e_in.const1(4-2) = '0' then
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ctrl_tmp.ctr <= std_ulogic_vector(unsigned(ctrl.ctr) - 1);
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end if;
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if ppc_bc_taken(e_in.const1(4 downto 0), e_in.const2(4 downto 0), e_in.cr, ctrl.ctr) = 1 then
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flush_out <= '1';
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f_out.redirect <= '1';
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f_out.redirect_nia <= std_ulogic_vector(signed(e_in.nia) + signed(e_in.read_data2));
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end if;
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when OP_BCLR =>
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if e_in.const1(4-2) = '0' then
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ctrl_tmp.ctr <= std_ulogic_vector(unsigned(ctrl.ctr) - 1);
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end if;
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if ppc_bc_taken(e_in.const1(4 downto 0), e_in.const2(4 downto 0), e_in.cr, ctrl.ctr) = 1 then
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flush_out <= '1';
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f_out.redirect <= '1';
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f_out.redirect_nia <= ctrl.lr(63 downto 2) & "00";
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end if;
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when OP_BCCTR =>
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if ppc_bcctr_taken(e_in.const1(4 downto 0), e_in.const2(4 downto 0), e_in.cr) = 1 then
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flush_out <= '1';
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f_out.redirect <= '1';
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f_out.redirect_nia <= ctrl.ctr(63 downto 2) & "00";
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end if;
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when OP_CMPB =>
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result := ppc_cmpb(e_in.read_data1, e_in.read_data2);
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result_en := 1;
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when OP_CMP =>
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v.e.write_cr_enable := '1';
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crnum := to_integer(unsigned(e_in.const1(2 downto 0)));
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v.e.write_cr_mask := num_to_fxm(crnum);
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for i in 0 to 7 loop
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lo := i*4;
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hi := lo + 3;
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v.e.write_cr_data(hi downto lo) := ppc_cmp(e_in.const2(0), e_in.read_data1, e_in.read_data2);
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end loop;
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when OP_CMPL =>
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v.e.write_cr_enable := '1';
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crnum := to_integer(unsigned(e_in.const1(2 downto 0)));
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v.e.write_cr_mask := num_to_fxm(crnum);
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for i in 0 to 7 loop
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lo := i*4;
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hi := lo + 3;
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v.e.write_cr_data(hi downto lo) := ppc_cmpl(e_in.const2(0), e_in.read_data1, e_in.read_data2);
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end loop;
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when OP_CNTLZW =>
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result := ppc_cntlzw(e_in.read_data1);
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result_en := 1;
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when OP_CNTTZW =>
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result := ppc_cnttzw(e_in.read_data1);
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result_en := 1;
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when OP_CNTLZD =>
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result := ppc_cntlzd(e_in.read_data1);
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result_en := 1;
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when OP_CNTTZD =>
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result := ppc_cnttzd(e_in.read_data1);
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result_en := 1;
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when OP_EXTSB =>
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result := ppc_extsb(e_in.read_data1);
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result_en := 1;
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when OP_EXTSH =>
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result := ppc_extsh(e_in.read_data1);
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result_en := 1;
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when OP_EXTSW =>
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result := ppc_extsw(e_in.read_data1);
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result_en := 1;
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when OP_EQV =>
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result := ppc_eqv(e_in.read_data1, e_in.read_data2);
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result_en := 1;
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when OP_ISEL =>
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crnum := to_integer(unsigned(e_in.const1));
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if e_in.cr(31-crnum) = '1' then
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result := e_in.read_data1;
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else
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result := e_in.read_data2;
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end if;
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result_en := 1;
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when OP_MFCTR =>
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result := ctrl.ctr;
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result_en := 1;
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when OP_MFLR =>
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result := ctrl.lr;
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result_en := 1;
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when OP_MFTB =>
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result := ctrl.tb;
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result_en := 1;
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when OP_MTCTR =>
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ctrl_tmp.ctr <= e_in.read_data1;
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when OP_MTLR =>
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ctrl_tmp.lr <= e_in.read_data1;
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when OP_MFCR =>
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result := x"00000000" & e_in.cr;
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result_en := 1;
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when OP_MFOCRF =>
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crnum := fxm_to_num(e_in.const1(7 downto 0));
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result := (others => '0');
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-- result((4*(7-crnum)+3) downto (4*(7-crnum))) := e_in.cr((4*(7-crnum)+3) downto (4*(7-crnum))); FIXME
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for i in 0 to 7 loop
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lo := (7-i)*4;
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hi := lo + 3;
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if crnum = i then
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result(hi downto lo) := e_in.cr(hi downto lo);
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end if;
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end loop;
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result_en := 1;
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when OP_MTCRF =>
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v.e.write_cr_enable := '1';
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v.e.write_cr_mask := e_in.const1(7 downto 0);
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v.e.write_cr_data := e_in.read_data1(31 downto 0);
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when OP_MTOCRF =>
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v.e.write_cr_enable := '1';
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-- We require one hot priority encoding here
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crnum := fxm_to_num(e_in.const1(7 downto 0));
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v.e.write_cr_mask := num_to_fxm(crnum);
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v.e.write_cr_data := e_in.read_data1(31 downto 0);
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when OP_NAND =>
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result := ppc_nand(e_in.read_data1, e_in.read_data2);
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result_en := 1;
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when OP_NEG =>
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result := ppc_neg(e_in.read_data1);
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result_en := 1;
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when OP_NOR =>
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result := ppc_nor(e_in.read_data1, e_in.read_data2);
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result_en := 1;
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when OP_OR =>
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result := ppc_or(e_in.read_data1, e_in.read_data2);
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result_en := 1;
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when OP_ORC =>
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result := ppc_orc(e_in.read_data1, e_in.read_data2);
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result_en := 1;
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when OP_POPCNTB =>
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result := ppc_popcntb(e_in.read_data1);
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result_en := 1;
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when OP_POPCNTW =>
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result := ppc_popcntw(e_in.read_data1);
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result_en := 1;
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when OP_POPCNTD =>
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result := ppc_popcntd(e_in.read_data1);
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result_en := 1;
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when OP_PRTYD =>
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result := ppc_prtyd(e_in.read_data1);
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result_en := 1;
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when OP_PRTYW =>
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result := ppc_prtyw(e_in.read_data1);
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result_en := 1;
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when OP_RLDCL =>
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result := ppc_rldcl(e_in.read_data1, e_in.read_data2, e_in.const2(5 downto 0));
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result_en := 1;
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when OP_RLDCR =>
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result := ppc_rldcr(e_in.read_data1, e_in.read_data2, e_in.const2(5 downto 0));
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result_en := 1;
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when OP_RLDICL =>
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result := ppc_rldicl(e_in.read_data1, e_in.const1(5 downto 0), e_in.const2(5 downto 0));
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result_en := 1;
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when OP_RLDICR =>
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result := ppc_rldicr(e_in.read_data1, e_in.const1(5 downto 0), e_in.const2(5 downto 0));
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result_en := 1;
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when OP_RLWNM =>
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result := ppc_rlwnm(e_in.read_data1, e_in.read_data2, e_in.const2(4 downto 0), e_in.const3(4 downto 0));
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result_en := 1;
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when OP_RLWINM =>
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result := ppc_rlwinm(e_in.read_data1, e_in.const1(4 downto 0), e_in.const2(4 downto 0), e_in.const3(4 downto 0));
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result_en := 1;
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when OP_RLDIC =>
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result := ppc_rldic(e_in.read_data1, e_in.const1(5 downto 0), e_in.const2(5 downto 0));
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result_en := 1;
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when OP_RLDIMI =>
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result := ppc_rldimi(e_in.read_data1, e_in.read_data2, e_in.const1(5 downto 0), e_in.const2(5 downto 0));
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result_en := 1;
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when OP_RLWIMI =>
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result := ppc_rlwimi(e_in.read_data1, e_in.read_data2, e_in.const1(4 downto 0), e_in.const2(4 downto 0), e_in.const3(4 downto 0));
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result_en := 1;
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when OP_SLD =>
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result := ppc_sld(e_in.read_data1, e_in.read_data2);
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result_en := 1;
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when OP_SLW =>
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result := ppc_slw(e_in.read_data1, e_in.read_data2);
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result_en := 1;
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when OP_SRAW =>
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result_with_carry := ppc_sraw(e_in.read_data1, e_in.read_data2);
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result := result_with_carry(63 downto 0);
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ctrl_tmp.carry <= result_with_carry(64);
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result_en := 1;
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when OP_SRAWI =>
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result_with_carry := ppc_srawi(e_in.read_data1, e_in.const1(5 downto 0));
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result := result_with_carry(63 downto 0);
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ctrl_tmp.carry <= result_with_carry(64);
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result_en := 1;
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when OP_SRAD =>
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result_with_carry := ppc_srad(e_in.read_data1, e_in.read_data2);
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result := result_with_carry(63 downto 0);
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ctrl_tmp.carry <= result_with_carry(64);
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result_en := 1;
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when OP_SRADI =>
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result_with_carry := ppc_sradi(e_in.read_data1, e_in.const1(5 downto 0));
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result := result_with_carry(63 downto 0);
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ctrl_tmp.carry <= result_with_carry(64);
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result_en := 1;
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when OP_SRD =>
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result := ppc_srd(e_in.read_data1, e_in.read_data2);
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result_en := 1;
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when OP_SRW =>
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result := ppc_srw(e_in.read_data1, e_in.read_data2);
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result_en := 1;
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when OP_SUBF =>
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result := ppc_subf(e_in.read_data1, e_in.read_data2);
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result_en := 1;
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when OP_SUBFC =>
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result_with_carry := ppc_subfe(e_in.read_data1, e_in.read_data2, ctrl.carry or not(e_in.input_carry));
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result := result_with_carry(63 downto 0);
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ctrl_tmp.carry <= result_with_carry(64) and e_in.output_carry;
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result_en := 1;
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when OP_XOR =>
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result := ppc_xor(e_in.read_data1, e_in.read_data2);
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result_en := 1;
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when OP_SIM_CONFIG =>
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-- bit 0 was used to select the microwatt console, which
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-- we no longer support.
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if SIM = true then
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result := x"0000000000000000";
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else
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result := x"0000000000000000";
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end if;
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result_en := 1;
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when OP_TDI =>
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-- Keep our test cases happy for now, ignore trap instructions
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report "OP_TDI FIXME";
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when OP_DIVDU =>
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if SIM = true then
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result := ppc_divdu(e_in.read_data1, e_in.read_data2);
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result_en := 1;
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else
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terminate_out <= '1';
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report "illegal";
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end if;
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when OP_DIVD =>
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if SIM = true then
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result := ppc_divd(e_in.read_data1, e_in.read_data2);
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result_en := 1;
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else
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terminate_out <= '1';
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report "illegal";
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end if;
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when OP_DIVWU =>
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if SIM = true then
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result := ppc_divwu(e_in.read_data1, e_in.read_data2);
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result_en := 1;
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else
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terminate_out <= '1';
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report "illegal";
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end if;
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when OP_DIVW =>
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if SIM = true then
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result := ppc_divw(e_in.read_data1, e_in.read_data2);
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result_en := 1;
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else
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terminate_out <= '1';
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report "illegal";
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end if;
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when others =>
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terminate_out <= '1';
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report "illegal";
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end case;
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if e_in.lr = '1' then
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ctrl_tmp.lr <= std_ulogic_vector(unsigned(e_in.nia) + 4);
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end if;
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if result_en = 1 then
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v.e.write_data := result;
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v.e.write_enable := '1';
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v.e.rc := e_in.rc;
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end if;
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end if;
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-- Update registers
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rin <= v;
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-- update outputs
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--f_out <= r.f;
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e_out <= r.e;
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end process;
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end architecture behaviour;
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