matthew1kalasky3
/
microwatt
forked from cores/microwatt
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity
You cannot select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
master
fpu-init
loadstore-init
core_debug-init
icache-unused-sig
icache-insn-u-state
dcache-unused-sig
unused-sig
divider-init
loadstore-pmu-init
icache-pmu-events
fpu-typo
less-fpga-init
caravel-mpw6-20220530
caravel-mpw5-20220323
caravel-mpw5-20220322
alt-reset-address
log2ceil-issue
fpu-constant
asic-3
boxarty-20211011
icbi-issue
orange-crab-freq
dcache-nc-fix
remove-potato-uart
cache-tlb-parameters-2
caravel-20210114
caravel-20210105
jtag-port-2
jtag-port
nia-debug
Branches Tags
${ item.name }
Create tag ${ searchTerm }
Create branch ${ searchTerm }
from '4bdfef9a20'
${ noResults }
microwatt/scripts
History
Benjamin Herrenschmidt 4bdfef9a20 mw_debug: Probe cable if unspecified 
Instead of defaulting to DigilentHS1

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 		3 years ago
..
fmt_log decode: Add a facility field to the instruction decode tables 4 years ago
mw_debug mw_debug: Probe cable if unspecified 3 years ago
bin2hex.py bin2hex: Make sure to generate little endian files 5 years ago
dependencies.py uart: Rename sim_uart.vhdl to sim_pp_uart.vhdl 4 years ago
gen_icache_tb.py icache_tb: Improve test and include test file 5 years ago
run_test.sh Dump CTR, LR and CR on sim termination, and update our tests 5 years ago
run_test_console.sh Add test cases for new exceptions and supervisor state 5 years ago
test_micropython.py Update micropython 5 years ago
test_micropython_long.py Update micropython 5 years ago
test_micropython_verilator.py makefile: Add some verilator micropython tests 3 years ago
test_micropython_verilator_long.py makefile: Add some verilator micropython tests 3 years ago
vhdltags Add VHDL TAGS 5 years ago