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375 lines
13 KiB
VHDL
375 lines
13 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.decode_types.all;
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use work.common.all;
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use work.helpers.all;
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use work.crhelpers.all;
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use work.insn_helpers.all;
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use work.ppc_fx_insns.all;
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entity execute1 is
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generic (
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SIM : boolean := false
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);
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port (
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clk : in std_logic;
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-- asynchronous
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flush_out : out std_ulogic;
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e_in : in Decode2ToExecute1Type;
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-- asynchronous
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f_out : out Execute1ToFetch1Type;
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e_out : out Execute1ToWritebackType;
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terminate_out : out std_ulogic
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);
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end entity execute1;
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architecture behaviour of execute1 is
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type reg_type is record
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--f : Execute1ToFetch1Type;
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e : Execute1ToWritebackType;
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end record;
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signal r, rin : reg_type;
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signal ctrl: ctrl_t := (carry => '0', others => (others => '0'));
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signal ctrl_tmp: ctrl_t := (carry => '0', others => (others => '0'));
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signal right_shift, rot_clear_left, rot_clear_right: std_ulogic;
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signal rotator_result: std_ulogic_vector(63 downto 0);
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signal rotator_carry: std_ulogic;
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signal logical_result: std_ulogic_vector(63 downto 0);
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signal countzero_result: std_ulogic_vector(63 downto 0);
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function decode_input_carry (carry_sel : carry_in_t; ca_in : std_ulogic) return std_ulogic is
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begin
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case carry_sel is
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when ZERO =>
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return '0';
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when CA =>
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return ca_in;
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when ONE =>
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return '1';
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end case;
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end;
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begin
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rotator_0: entity work.rotator
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port map (
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rs => e_in.read_data3,
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ra => e_in.read_data1,
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shift => e_in.read_data2(6 downto 0),
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insn => e_in.insn,
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is_32bit => e_in.is_32bit,
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right_shift => right_shift,
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arith => e_in.is_signed,
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clear_left => rot_clear_left,
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clear_right => rot_clear_right,
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result => rotator_result,
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carry_out => rotator_carry
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);
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logical_0: entity work.logical
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port map (
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rs => e_in.read_data3,
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rb => e_in.read_data2,
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op => e_in.insn_type,
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invert_in => e_in.invert_a,
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invert_out => e_in.invert_out,
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result => logical_result
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);
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countzero_0: entity work.zero_counter
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port map (
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rs => e_in.read_data3,
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count_right => e_in.insn(10),
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is_32bit => e_in.is_32bit,
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result => countzero_result
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);
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execute1_0: process(clk)
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begin
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if rising_edge(clk) then
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r <= rin;
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ctrl <= ctrl_tmp;
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end if;
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end process;
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execute1_1: process(all)
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variable v : reg_type;
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variable a_inv : std_ulogic_vector(63 downto 0);
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variable result : std_ulogic_vector(63 downto 0);
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variable newcrf : std_ulogic_vector(3 downto 0);
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variable result_with_carry : std_ulogic_vector(64 downto 0);
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variable result_en : integer;
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variable crnum : integer;
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variable scrnum : integer;
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variable lo, hi : integer;
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variable sh, mb, me : std_ulogic_vector(5 downto 0);
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variable sh32, mb32, me32 : std_ulogic_vector(4 downto 0);
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variable bo, bi : std_ulogic_vector(4 downto 0);
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variable bf, bfa : std_ulogic_vector(2 downto 0);
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variable l : std_ulogic;
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begin
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result := (others => '0');
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result_with_carry := (others => '0');
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result_en := 0;
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newcrf := (others => '0');
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v := r;
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v.e := Execute1ToWritebackInit;
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--v.f := Execute1ToFetch1TypeInit;
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ctrl_tmp <= ctrl;
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-- FIXME: run at 512MHz not core freq
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ctrl_tmp.tb <= std_ulogic_vector(unsigned(ctrl.tb) + 1);
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terminate_out <= '0';
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f_out <= Execute1ToFetch1TypeInit;
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-- rotator control signals
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right_shift <= '1' when e_in.insn_type = OP_SHR else '0';
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rot_clear_left <= '1' when e_in.insn_type = OP_RLC or e_in.insn_type = OP_RLCL else '0';
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rot_clear_right <= '1' when e_in.insn_type = OP_RLC or e_in.insn_type = OP_RLCR else '0';
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if e_in.valid = '1' then
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v.e.valid := '1';
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v.e.write_reg := e_in.write_reg;
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v.e.write_len := x"8";
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v.e.sign_extend := '0';
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case_0: case e_in.insn_type is
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when OP_ILLEGAL =>
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terminate_out <= '1';
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report "illegal";
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when OP_NOP =>
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-- Do nothing
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when OP_ADD =>
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if e_in.invert_a = '0' then
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a_inv := e_in.read_data1;
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else
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a_inv := not e_in.read_data1;
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end if;
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result_with_carry := ppc_adde(a_inv, e_in.read_data2, decode_input_carry(e_in.input_carry, ctrl.carry));
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result := result_with_carry(63 downto 0);
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if e_in.output_carry then
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ctrl_tmp.carry <= result_with_carry(64);
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end if;
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result_en := 1;
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when OP_AND | OP_OR | OP_XOR =>
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result := logical_result;
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result_en := 1;
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when OP_B =>
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f_out.redirect <= '1';
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if (insn_aa(e_in.insn)) then
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f_out.redirect_nia <= std_ulogic_vector(signed(e_in.read_data2));
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else
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f_out.redirect_nia <= std_ulogic_vector(signed(e_in.nia) + signed(e_in.read_data2));
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end if;
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when OP_BC =>
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bo := insn_bo(e_in.insn);
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bi := insn_bi(e_in.insn);
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if bo(4-2) = '0' then
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ctrl_tmp.ctr <= std_ulogic_vector(unsigned(ctrl.ctr) - 1);
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end if;
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if ppc_bc_taken(bo, bi, e_in.cr, ctrl.ctr) = 1 then
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f_out.redirect <= '1';
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if (insn_aa(e_in.insn)) then
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f_out.redirect_nia <= std_ulogic_vector(signed(e_in.read_data2));
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else
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f_out.redirect_nia <= std_ulogic_vector(signed(e_in.nia) + signed(e_in.read_data2));
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end if;
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end if;
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when OP_BCREG =>
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-- bits 10 and 6 distinguish between bclr, bcctr and bctar
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bo := insn_bo(e_in.insn);
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bi := insn_bi(e_in.insn);
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if bo(4-2) = '0' and e_in.insn(10) = '0' then
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ctrl_tmp.ctr <= std_ulogic_vector(unsigned(ctrl.ctr) - 1);
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end if;
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if ppc_bc_taken(bo, bi, e_in.cr, ctrl.ctr) = 1 then
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f_out.redirect <= '1';
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if e_in.insn(10) = '0' then
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f_out.redirect_nia <= ctrl.lr(63 downto 2) & "00";
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else
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f_out.redirect_nia <= ctrl.ctr(63 downto 2) & "00";
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end if;
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end if;
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when OP_CMPB =>
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result := ppc_cmpb(e_in.read_data3, e_in.read_data2);
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result_en := 1;
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when OP_CMP =>
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bf := insn_bf(e_in.insn);
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l := insn_l(e_in.insn);
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v.e.write_cr_enable := '1';
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crnum := to_integer(unsigned(bf));
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v.e.write_cr_mask := num_to_fxm(crnum);
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for i in 0 to 7 loop
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lo := i*4;
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hi := lo + 3;
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v.e.write_cr_data(hi downto lo) := ppc_cmp(l, e_in.read_data1, e_in.read_data2);
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end loop;
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when OP_CMPL =>
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bf := insn_bf(e_in.insn);
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l := insn_l(e_in.insn);
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v.e.write_cr_enable := '1';
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crnum := to_integer(unsigned(bf));
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v.e.write_cr_mask := num_to_fxm(crnum);
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for i in 0 to 7 loop
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lo := i*4;
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hi := lo + 3;
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v.e.write_cr_data(hi downto lo) := ppc_cmpl(l, e_in.read_data1, e_in.read_data2);
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end loop;
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when OP_CNTZ =>
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result := countzero_result;
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result_en := 1;
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when OP_EXTS =>
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v.e.write_len := e_in.data_len;
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v.e.sign_extend := '1';
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result := e_in.read_data3;
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result_en := 1;
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when OP_ISEL =>
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crnum := to_integer(unsigned(insn_bc(e_in.insn)));
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if e_in.cr(31-crnum) = '1' then
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result := e_in.read_data1;
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else
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result := e_in.read_data2;
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end if;
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result_en := 1;
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when OP_MCRF =>
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bf := insn_bf(e_in.insn);
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bfa := insn_bfa(e_in.insn);
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v.e.write_cr_enable := '1';
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crnum := to_integer(unsigned(bf));
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scrnum := to_integer(unsigned(bfa));
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v.e.write_cr_mask := num_to_fxm(crnum);
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for i in 0 to 7 loop
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lo := (7-i)*4;
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hi := lo + 3;
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if i = scrnum then
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newcrf := e_in.cr(hi downto lo);
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end if;
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end loop;
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for i in 0 to 7 loop
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lo := i*4;
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hi := lo + 3;
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v.e.write_cr_data(hi downto lo) := newcrf;
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end loop;
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when OP_MFSPR =>
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if std_match(e_in.insn(20 downto 11), "0100100000") then
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result := ctrl.ctr;
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result_en := 1;
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elsif std_match(e_in.insn(20 downto 11), "0100000000") then
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result := ctrl.lr;
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result_en := 1;
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elsif std_match(e_in.insn(20 downto 11), "0110001000") then
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result := ctrl.tb;
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result_en := 1;
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end if;
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when OP_MFCR =>
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if e_in.insn(20) = '0' then
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-- mfcr
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result := x"00000000" & e_in.cr;
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else
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-- mfocrf
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crnum := fxm_to_num(insn_fxm(e_in.insn));
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result := (others => '0');
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for i in 0 to 7 loop
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lo := (7-i)*4;
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hi := lo + 3;
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if crnum = i then
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result(hi downto lo) := e_in.cr(hi downto lo);
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end if;
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end loop;
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end if;
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result_en := 1;
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when OP_MTCRF =>
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v.e.write_cr_enable := '1';
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if e_in.insn(20) = '0' then
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-- mtcrf
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v.e.write_cr_mask := insn_fxm(e_in.insn);
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else
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-- mtocrf: We require one hot priority encoding here
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crnum := fxm_to_num(insn_fxm(e_in.insn));
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v.e.write_cr_mask := num_to_fxm(crnum);
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end if;
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v.e.write_cr_data := e_in.read_data3(31 downto 0);
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when OP_MTSPR =>
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if std_match(e_in.insn(20 downto 11), "0100100000") then
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ctrl_tmp.ctr <= e_in.read_data3;
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elsif std_match(e_in.insn(20 downto 11), "0100000000") then
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ctrl_tmp.lr <= e_in.read_data3;
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end if;
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when OP_NEG =>
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result := ppc_neg(e_in.read_data1);
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result_en := 1;
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when OP_POPCNTB =>
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result := ppc_popcntb(e_in.read_data3);
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result_en := 1;
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when OP_POPCNTW =>
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result := ppc_popcntw(e_in.read_data3);
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result_en := 1;
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when OP_POPCNTD =>
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result := ppc_popcntd(e_in.read_data3);
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result_en := 1;
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when OP_PRTYD =>
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result := ppc_prtyd(e_in.read_data3);
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result_en := 1;
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when OP_PRTYW =>
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result := ppc_prtyw(e_in.read_data3);
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result_en := 1;
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when OP_RLC | OP_RLCL | OP_RLCR | OP_SHL | OP_SHR =>
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result := rotator_result;
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if e_in.output_carry = '1' then
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ctrl_tmp.carry <= rotator_carry;
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end if;
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result_en := 1;
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when OP_SIM_CONFIG =>
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-- bit 0 was used to select the microwatt console, which
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-- we no longer support.
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if SIM = true then
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result := x"0000000000000000";
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else
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result := x"0000000000000000";
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end if;
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result_en := 1;
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when OP_TDI =>
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-- Keep our test cases happy for now, ignore trap instructions
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report "OP_TDI FIXME";
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when others =>
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terminate_out <= '1';
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report "illegal";
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end case;
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if e_in.lr = '1' then
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ctrl_tmp.lr <= std_ulogic_vector(unsigned(e_in.nia) + 4);
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end if;
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if result_en = 1 then
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v.e.write_data := result;
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v.e.write_enable := '1';
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v.e.rc := e_in.rc;
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end if;
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end if;
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-- Update registers
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rin <= v;
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-- update outputs
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--f_out <= r.f;
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e_out <= r.e;
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flush_out <= f_out.redirect;
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end process;
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end architecture behaviour;
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