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microwatt/litedram/extras
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Benjamin Herrenschmidt 599fad117b litedram: Remove old "VexRiscV" based initializations 
Support for this has bitrotted and would require refactoring of L2 to
be brought back. It's also not really needed anymore now that we ship
pre-generated litedram and that LiteX supports what we do.

So take it out, which simplifies some of the scripts as well. This also
fixes up CSR alignment the sim model.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 		4 years ago
..
fusesoc-add-files.py litedram: Remove old "VexRiscV" based initializations 4 years ago
litedram-wrapper-l2.vhdl litedram: Remove old "VexRiscV" based initializations 4 years ago
sim_dram_verilate.mk litedram: Add simulation support 4 years ago
sim_litedram.vhdl litedram: Add simulation support 4 years ago
sim_litedram_c.cpp litedram: Add simulation support 4 years ago
wave.gtkw litedram: Add an L2 cache with store queue 4 years ago
wave.opt litedram: Add an L2 cache with store queue 4 years ago
wave_tb.gtkw litedram: Test bench 4 years ago