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microwatt/fpga
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Michael Neuling 5aaa63ee3b Add PLL for ECP5 device 
Means we can synthesize at 40Mhz (where we currently make timing) and
our UART still works at 115200 baud.

Tested working hello world unmodified with ECP5 eval board. Orange
Crab is updated but is untested.

Signed-off-by: Michael Neuling <mikey@neuling.org>
..
LICENSE Initial import of microwatt
arty_a7.xdc uart: Import and hook up opencore 16550 compatible UART
clk_gen_bypass.vhd Fix clk_gen_bypass
clk_gen_ecp5.vhd Add PLL for ECP5 device
clk_gen_mcmm.vhd Improve PLL/MMCM clocks configuration
clk_gen_plle2.vhd Improve PLL/MMCM clocks configuration
cmod_a7-35.xdc Add SPI configuration to Xilinx constraint files
firmware.hex Add a few more FPGA related files
hello_world.hex hello_world: Use new headers and frequency from syscon
main_bram.vhdl Fix some ghdlsynth issues with fpga_bram
nexys-video.xdc spi: Add SPI Flash controller
nexys_a7.xdc Add SPI configuration to Xilinx constraint files
pp_fifo.vhd pp_fifo: Fix full fifo losing all data on simultaneous push & pop
pp_soc_uart.vhd uart: Remove combinational loops on ack and stall signal
pp_utilities.vhd Initial import of microwatt
soc_reset.vhdl soc_reset: Use counters, add synchronizers
soc_reset_tb.vhdl Exit cleanly from testbench on success
top-arty.vhdl uart: Make 16550 the default
top-generic.vhdl uart: Make 16550 the default
top-nexys-video.vhdl uart: Make 16550 the default