You cannot select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
microwatt/litedram/extras
Benjamin Herrenschmidt b58ff724f6 litedram: Add stash buffer to the L2 cache wishbone interface
This breaks the long stall signal coming back to the processor
and helps improve overall timing.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
..
fusesoc-add-files.py
litedram-wrapper-l2.vhdl litedram: Add stash buffer to the L2 cache wishbone interface 5 years ago
sim_dram_verilate.mk
sim_litedram.vhdl
sim_litedram_c.cpp
wave.gtkw
wave.opt
wave_tb.gtkw