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Benjamin Herrenschmidt 9961d70dfb Improve PLL/MMCM clocks configuration 
We can now pass both the input clock and target clock frequency
via generics. Add support for both 50Mhz and 100Mhz target freqs
for both cases.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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LICENSE
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arty_a7.xdc fpga: Arty A7's don't need multiple filesets
clk_gen_bypass.vhd Fix clk_gen_bypass
clk_gen_mcmm.vhd Improve PLL/MMCM clocks configuration
clk_gen_plle2.vhd Improve PLL/MMCM clocks configuration
cmod_a7-35.xdc Cmod A7-35 support
firmware.hex
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hello_world.hex
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mw_soc_memory.vhdl SOC memory wishbone should clear ACK regardless of STB
nexys-video.xdc Rename a few reset signals
nexys_a7.xdc Merge pull request from antonblanchard/reset-rework2
pp_fifo.vhd
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pp_soc_uart.vhd
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pp_utilities.vhd
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soc_reset.vhdl Rework SOC reset
soc_reset_tb.vhdl Rework SOC reset
toplevel.vhdl Improve PLL/MMCM clocks configuration