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Benjamin Herrenschmidt 9961d70dfb Improve PLL/MMCM clocks configuration ... We can now pass both the input clock and target clock frequency via generics. Add support for both 50Mhz and 100Mhz target freqs for both cases. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>		5 years ago
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LICENSE	…
arty_a7.xdc	fpga: Arty A7's don't need multiple filesets	5 years ago
clk_gen_bypass.vhd	Fix clk_gen_bypass	5 years ago
clk_gen_mcmm.vhd	Improve PLL/MMCM clocks configuration	5 years ago
clk_gen_plle2.vhd	Improve PLL/MMCM clocks configuration	5 years ago
cmod_a7-35.xdc	Cmod A7-35 support	5 years ago
firmware.hex	Add a few more FPGA related files	5 years ago
hello_world.hex	Rebuild hello world assuming a 50MHz clock	5 years ago
mw_soc_memory.vhdl	SOC memory wishbone should clear ACK regardless of STB	5 years ago
nexys-video.xdc	Rename a few reset signals	5 years ago
nexys_a7.xdc	Merge pull request #20 from antonblanchard/reset-rework2	5 years ago
pp_fifo.vhd	…
pp_soc_uart.vhd	…
pp_utilities.vhd	…
soc_reset.vhdl	Rework SOC reset	5 years ago
soc_reset_tb.vhdl	Rework SOC reset	5 years ago
toplevel.vhdl	Improve PLL/MMCM clocks configuration	5 years ago