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Raptor Engineering Development Team fcb783a0fb Extend LiteDRAM VHDL wrapper to allow more than one clock line 
This is necessary for the upcoming Arctic Tern system enablement,
since Arctic Tern uses two DRAM devices and a separate clock line
is routed to each device.  LiteX handles this behavior correctly,
therefore we assume other hardware exists that uses a similar
DRAM clock design.

Updates from Mikey to fix some compile issues.

Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Signed-off-by: Michael Neuling <mikey@neuling.org>
..
extras Extend LiteDRAM VHDL wrapper to allow more than one clock line
gen-src litedram: Add orangecrab-85-0.2 target
generated litedram: Add orangecrab-85-0.2 target
litedram.core litedram: Add basic support for LiteX LiteDRAM