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fpu-init
loadstore-init
core_debug-init
icache-unused-sig
icache-insn-u-state
dcache-unused-sig
unused-sig
divider-init
loadstore-pmu-init
icache-pmu-events
fpu-typo
less-fpga-init
caravel-mpw6-20220530
caravel-mpw5-20220323
caravel-mpw5-20220322
alt-reset-address
log2ceil-issue
fpu-constant
asic-3
boxarty-20211011
icbi-issue
orange-crab-freq
dcache-nc-fix
remove-potato-uart
cache-tlb-parameters-2
caravel-20210114
caravel-20210105
jtag-port-2
jtag-port
nia-debug
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microwatt/scripts
History
Paul Mackerras 3340d8aa9f mw_debug: Add support for reading GSPRs and writing memory 
This adds a "gpr" command for reading 1 or more GPRs/fast SPRs,
and a "mw" command for writing an 8-byte value to memory.  It also
adds an "icreset" command for resetting the instruction cache
and fixes the "creset" command to actually reset the core instead
of starting it.  The MSR is now printed along with the NIA in the
status information.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
 		5 years ago
..
mw_debug mw_debug: Add support for reading GSPRs and writing memory 5 years ago
bin2hex.py Move bin2hex.py to scripts/ 5 years ago
dependencies.py Improve dependencies.py and add a --synth option 5 years ago
gen_icache_tb.py icache_tb: Improve test and include test file 5 years ago
run_test.sh Dump CTR, LR and CR on sim termination, and update our tests 5 years ago
run_test_console.sh Add test cases for new exceptions and supervisor state 5 years ago
test_micropython.py Update micropython 5 years ago
test_micropython_long.py Update micropython 5 years ago
verific.sh Fix verific script with new VHDL files 5 years ago
vhdltags Add VHDL TAGS 5 years ago