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cc4dcb3597
This adds an SPI flash controller which supports direct memory-mapped access to the flash along with a manual mode to send commands. The direct mode can be set via generic to default to single wire or quad mode. The controller supports normal, dual and quad accesses with configurable commands, clock divider, dummy clocks etc... The SPI clock can be an even divider of sys_clk starting at 2 (so max 50Mhz with our typical Arty designs). A flash offset is carried via generics to syscon to tell SW about which portion of the flash is reserved for the FPGA bitfile. There is currently no plumbing to make the CPU reset past that address (TBD). Note: Operating at 50Mhz has proven unreliable without adding some delay to the sampling of the input data. I'm working in improving this, in the meantime, I'm leaving the default set at 25 Mhz. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> |
4 years ago | |
|---|---|---|
| .. | ||
| LICENSE | 5 years ago | |
| arty_a7.xdc | 4 years ago | |
| clk_gen_bypass.vhd | 5 years ago | |
| clk_gen_mcmm.vhd | 5 years ago | |
| clk_gen_plle2.vhd | 5 years ago | |
| cmod_a7-35.xdc | 5 years ago | |
| firmware.hex | 5 years ago | |
| hello_world.hex | 5 years ago | |
| main_bram.vhdl | 5 years ago | |
| nexys-video.xdc | 4 years ago | |
| nexys_a7.xdc | 5 years ago | |
| pp_fifo.vhd | 5 years ago | |
| pp_soc_uart.vhd | 5 years ago | |
| pp_utilities.vhd | 5 years ago | |
| soc_reset.vhdl | 5 years ago | |
| soc_reset_tb.vhdl | 5 years ago | |
| top-arty.vhdl | 4 years ago | |
| top-generic.vhdl | 4 years ago | |
| top-nexys-video.vhdl | 4 years ago | |