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microwatt/litedram/gen-src/sdram_init
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Benjamin Herrenschmidt 6fe077910b litedram: Add simulation support 
This adds a simulated litedram model along with the necessary
Makefile gunk to verilate it and wrap it for use by ghdl.

The core_dram_tb test bench is a variant of core_tb with
LiteDRAM simulated. It's not built by default, an explicit

make core_dram_tb

is necessary as to not require verilator to be installed for
the normal build process (also it's slow'ish).

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 		5 years ago
..
include litedram: Add simulation support 5 years ago
libc litedram: Add support for Microwatt-initialized controller 5 years ago
Makefile litedram: Add simulation support 5 years ago
bin2hex.py litedram: Add basic support for LiteX LiteDRAM 5 years ago
head.S soc: Rework interconnect 5 years ago
main.c litedram: Remove init delays 5 years ago
sdram_init.lds.S soc: Rework interconnect 5 years ago