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fpu-init
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icache-unused-sig
icache-insn-u-state
dcache-unused-sig
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divider-init
loadstore-pmu-init
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caravel-mpw6-20220530
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alt-reset-address
log2ceil-issue
fpu-constant
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boxarty-20211011
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microwatt/litedram/extras
History
Benjamin Herrenschmidt a93d9e77c9 litedram: Remove remnants of riscv-inits 
We still had some wires bringing an extra serial port out of
litedram for the built-in riscv processor. This is all gone now
so take them out.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 		5 years ago
..
fusesoc-add-files.py litedram: Remove old "VexRiscV" based initializations 5 years ago
litedram-wrapper-l2.vhdl litedram: Remove remnants of riscv-inits 5 years ago
sim_dram_verilate.mk litedram: Add simulation support 5 years ago
sim_litedram.vhdl litedram: Add simulation support 5 years ago
sim_litedram_c.cpp litedram: Add simulation support 5 years ago
wave.gtkw litedram: Add an L2 cache with store queue 5 years ago
wave.opt litedram: Add an L2 cache with store queue 5 years ago
wave_tb.gtkw litedram: Test bench 5 years ago