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Paul Mackerras 290b05f97d core: Implement the maddhd, maddhdu and maddld instructions ... These instructions use major opcode 4 and have a third GPR input operand, so we need a decode table for major opcode 4 and some plumbing to get the RC register operand read. The multiply-add instructions use the same insn_type_t values as the regular multiply instructions, and we distinguish in execute1 by looking at the major opcode. This turns out to be convenient because we don't have to add any cases in the code that handles the output of the multiplier, and it frees up some insn_type_t values. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>		4 years ago
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fmt_log	core: Implement the maddhd, maddhdu and maddld instructions	4 years ago
mw_debug	Add core logging	5 years ago
bin2hex.py	bin2hex: Make sure to generate little endian files	5 years ago
dependencies.py	uart: Rename sim_uart.vhdl to sim_pp_uart.vhdl	4 years ago
gen_icache_tb.py	icache_tb: Improve test and include test file	5 years ago
run_test.sh	Dump CTR, LR and CR on sim termination, and update our tests	5 years ago
run_test_console.sh	Add test cases for new exceptions and supervisor state	5 years ago
test_micropython.py	Update micropython	5 years ago
test_micropython_long.py	Update micropython	5 years ago
vhdltags	Add VHDL TAGS	5 years ago