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7560e8f2ff
When using litedram, request a much longer PLL reset. This seems to help get rid of all the grabled output after config. Also use the clean system_rst out of litedram as our source of reset for the rest of the SoC (it is synchronized with system_clk and takes pll_locked into account already) |
5 years ago | |
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LICENSE | 5 years ago | |
arty_a7.xdc | 5 years ago | |
clk_gen_bypass.vhd | 5 years ago | |
clk_gen_mcmm.vhd | 5 years ago | |
clk_gen_plle2.vhd | 5 years ago | |
cmod_a7-35.xdc | 5 years ago | |
firmware.hex | 5 years ago | |
hello_world.hex | 5 years ago | |
main_bram.vhdl | 5 years ago | |
nexys-video.xdc | 5 years ago | |
nexys_a7.xdc | 5 years ago | |
pp_fifo.vhd | 5 years ago | |
pp_soc_uart.vhd | 5 years ago | |
pp_utilities.vhd | 5 years ago | |
soc_reset.vhdl | 5 years ago | |
soc_reset_tb.vhdl | 5 years ago | |
top-arty.vhdl | 5 years ago | |
top-generic.vhdl | 5 years ago | |
top-nexys-video.vhdl | 5 years ago |