forked from cores/microwatt
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60e5f7b958
No cells matched 'get_cells -hierarchical -filter {NAME =~*/spi_rxtx/dat_i_l*}'. [build/microwatt_0/src/microwatt_0/fpga/arty_a7.xdc:42] The signal is in it's own process so the net name ends up being spi_rxtx/input_delay_1.dat_i_l_reg. After this change the log shows: Applied set_property IOB = TRUE for soc0/\spiflash_gen.spiflash /spi_rxtx/\input_delay_1.dat_i_l_reg . (constraint file fpga/arty_a7.xdc, line 42). Applied set_property IOB = TRUE for soc0/\spiflash_gen.spiflash /spi_rxtx/\input_delay_1.dat_i_l_reg . (constraint file fpga/arty_a7.xdc, line 42). Applied set_property IOB = TRUE for soc0/\spiflash_gen.spiflash /spi_rxtx/\input_delay_1.dat_i_l_reg . (constraint file fpga/arty_a7.xdc, line 42). Applied set_property IOB = TRUE for soc0/\spiflash_gen.spiflash /spi_rxtx/\input_delay_1.dat_i_l_reg . (constraint file fpga/arty_a7.xdc, line 42). Signed-off-by: Joel Stanley <joel@jms.id.au> |
5 years ago | |
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.. | ||
LICENSE | ||
arty_a7.xdc | 5 years ago | |
clk_gen_bypass.vhd | ||
clk_gen_mcmm.vhd | ||
clk_gen_plle2.vhd | ||
cmod_a7-35.xdc | ||
firmware.hex | ||
hello_world.hex | ||
main_bram.vhdl | ||
nexys-video.xdc | 5 years ago | |
nexys_a7.xdc | ||
pp_fifo.vhd | 5 years ago | |
pp_soc_uart.vhd | 5 years ago | |
pp_utilities.vhd | ||
soc_reset.vhdl | 5 years ago | |
soc_reset_tb.vhdl | 5 years ago | |
top-arty.vhdl | 5 years ago | |
top-generic.vhdl | 5 years ago | |
top-nexys-video.vhdl | 5 years ago |