You cannot select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
microwatt/fpga
Anton Blanchard 7aaed5abd5 fifo: Reformat
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
..
LICENSE Initial import of microwatt 5 years ago
arty_a7.xdc fpga: Arty A7's don't need multiple filesets 5 years ago
clk_gen_bypass.vhd Fix clk_gen_bypass 5 years ago
clk_gen_mcmm.vhd Improve PLL/MMCM clocks configuration 5 years ago
clk_gen_plle2.vhd Improve PLL/MMCM clocks configuration 5 years ago
cmod_a7-35.xdc Cmod A7-35 support 5 years ago
firmware.hex Add a few more FPGA related files 5 years ago
hello_world.hex Rebuild hello world assuming a 50MHz clock 5 years ago
mw_soc_memory.vhdl SOC memory wishbone should clear ACK regardless of STB 5 years ago
nexys-video.xdc Rename a few reset signals 5 years ago
nexys_a7.xdc Merge pull request #20 from antonblanchard/reset-rework2 5 years ago
pp_fifo.vhd fifo: Reformat 5 years ago
pp_soc_uart.vhd Initial import of microwatt 5 years ago
pp_utilities.vhd Initial import of microwatt 5 years ago
soc_reset.vhdl Rework SOC reset 5 years ago
soc_reset_tb.vhdl Rework SOC reset 5 years ago
toplevel.vhdl Improve PLL/MMCM clocks configuration 5 years ago