matthew1kalasky3
/
microwatt
forked from cores/microwatt
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity
You cannot select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
master
fpu-init
loadstore-init
core_debug-init
icache-unused-sig
icache-insn-u-state
dcache-unused-sig
unused-sig
divider-init
loadstore-pmu-init
icache-pmu-events
fpu-typo
less-fpga-init
caravel-mpw6-20220530
caravel-mpw5-20220323
caravel-mpw5-20220322
alt-reset-address
log2ceil-issue
fpu-constant
asic-3
boxarty-20211011
icbi-issue
orange-crab-freq
dcache-nc-fix
remove-potato-uart
cache-tlb-parameters-2
caravel-20210114
caravel-20210105
jtag-port-2
jtag-port
nia-debug
Branches Tags
${ item.name }
Create tag ${ searchTerm }
Create branch ${ searchTerm }
from '8366710217'
${ noResults }
microwatt/litedram/gen-src/sdram_init
History
Benjamin Herrenschmidt 8366710217 liteeth: Hook up LiteX LiteEth ethernet controller 
Currently only generated for Arty.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 		5 years ago
..
include spi: Add booting from flash to litedram init 5 years ago
libc litedram: Add support for Microwatt-initialized controller 5 years ago
Makefile litedram: Add simulation support 5 years ago
bin2hex.py litedram: Add basic support for LiteX LiteDRAM 5 years ago
head.S spi: Add booting from flash to litedram init 5 years ago
main.c liteeth: Hook up LiteX LiteEth ethernet controller 5 years ago
sdram_init.lds.S soc: Rework interconnect 5 years ago